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56c3aa9ab9
The QEMU emulation of m68k does not support DMA timer, the only timer that is supported is the PIT timer. Implement trivial PIT timer support for m68k. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
169 lines
3.6 KiB
C
169 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <init.h>
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#include <irq_func.h>
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#include <time.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <asm/timer.h>
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#include <asm/immap.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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static volatile ulong timestamp = 0;
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#ifndef CFG_SYS_WATCHDOG_FREQ
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#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
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#endif
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#if CONFIG_IS_ENABLED(MCFTMR)
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#ifndef CFG_SYS_UDELAY_BASE
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# error "uDelay base not defined!"
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#endif
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#if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK)
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# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
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#endif
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extern void dtimer_intr_setup(void);
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void __udelay(unsigned long usec)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE);
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uint start, now, tmp;
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 3 as timebase clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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timerp->tcn = 0;
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/* set period to 1 us */
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timerp->tmr =
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CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
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DTIM_DTMR_RST_EN;
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start = now = timerp->tcn;
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while (now < start + tmp)
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now = timerp->tcn;
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}
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}
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void dtimer_interrupt(void *not_used)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
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/* check for timer interrupt asserted */
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if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) {
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timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
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timestamp++;
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#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
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if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) {
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schedule();
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}
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#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
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return;
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}
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}
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int timer_init(void)
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{
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volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
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timestamp = 0;
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timerp->tcn = 0;
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timerp->trr = 0;
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/* Set up TIMER 4 as clock */
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timerp->tmr = DTIM_DTMR_RST_RST;
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/* initialize and enable timer interrupt */
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irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
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timerp->tcn = 0;
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timerp->trr = 1000; /* Interrupt every ms */
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dtimer_intr_setup();
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
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DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
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return 0;
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}
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ulong get_timer(ulong base)
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{
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return (timestamp - base);
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}
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On M68K it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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#else
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static u64 timer64 __section(".data");
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static u16 timer16 __section(".data");
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uint64_t __weak get_ticks(void)
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{
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volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
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u16 val = ~timerp->pcntr;
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if (timer16 > val)
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timer64 += 0xffff - timer16 + val;
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else
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timer64 += val - timer16;
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timer16 = val;
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return timer64;
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}
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/* PIT timer */
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int timer_init(void)
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{
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volatile pit_t *timerp = (pit_t *) (CFG_SYS_UDELAY_BASE);
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timer16 = 0;
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timer64 = 0;
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/* Set up PIT as timebase clock */
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timerp->pmr = 0xffff;
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timerp->pcsr = PIT_PCSR_EN | PIT_PCSR_OVW;
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return 0;
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}
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#endif /* CONFIG_MCFTMR */
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unsigned long usec2ticks(unsigned long usec)
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{
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return get_timer(usec);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On M68K it returns the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return CONFIG_SYS_HZ;
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}
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