Rick Chen e8e39597a3 riscv: cpu: Add nx25 to support RISC-V ... Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>		2018-01-12 08:05:12 -05:00
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cpu.c	riscv: cpu: Add nx25 to support RISC-V	2018-01-12 08:05:12 -05:00
Makefile	riscv: cpu: Add nx25 to support RISC-V	2018-01-12 08:05:12 -05:00
start.S	riscv: cpu: Add nx25 to support RISC-V	2018-01-12 08:05:12 -05:00
u-boot.lds	riscv: cpu: Add nx25 to support RISC-V	2018-01-12 08:05:12 -05:00