mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 12:33:41 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
890 lines
26 KiB
C
890 lines
26 KiB
C
/*********************************************************
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* $Id
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*
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* copyright @ Motorola, 1999
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*********************************************************/
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#include "i2o.h"
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extern unsigned int load_runtime_reg( unsigned int eumbbar, unsigned int reg );
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#pragma Alias( load_runtime_reg, "load_runtime_reg" );
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extern void store_runtime_reg( unsigned int eumbbar, unsigned int reg, unsigned int val );
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#pragma Alias( store_runtime_reg, "store_runtime_reg" );
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typedef struct _fifo_stat
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{
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QUEUE_SIZE qsz;
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unsigned int qba;
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} FIFOSTAT;
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FIFOSTAT fifo_stat = { QSIZE_4K, 0xffffffff };
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/**********************************************************************************
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* function: I2OMsgEnable
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*
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* description: Enable the interrupt associated with in/out bound msg
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* return I2OSUCCESS if no error, otherwise return I2OMSGINVALID.
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*
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* All previously enabled interrupts are preserved.
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* note:
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* Inbound message interrupt generated by PCI master and serviced by local processor
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* Outbound message interrupt generated by local processor and serviced by PCI master
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*
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* local processor needs to enable its inbound interrupts it wants to handle(LOCAL)
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* PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE)
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************************************************************************************/
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I2OSTATUS I2OMsgEnable ( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned char n ) /* b'1' - msg 0
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* b'10'- msg 1
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* b'11'- both
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*/
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{
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unsigned int reg, val;
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if ( ( n & 0x3 ) == 0 )
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{
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/* neither msg 0, nor msg 1 */
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return I2OMSGINVALID;
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}
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n = (~n) & 0x3;
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/* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base
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* LOCAL : enable local inbound message, eumbbar as base
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*/
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reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
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val = load_runtime_reg( base, reg );
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val &= 0xfffffffc; /* masked out the msg interrupt bits */
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val |= n; /* LSB are the one we want */
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store_runtime_reg( base, reg, val );
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return I2OSUCCESS;
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}
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/*********************************************************************************
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* function: I2OMsgDisable
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*
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* description: Disable the interrupt associated with in/out bound msg
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* Other previously enabled interrupts are preserved.
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* return I2OSUCCESS if no error otherwise return I2OMSGINVALID
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*
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* note:
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* local processor needs to disable its inbound interrupts it is not interested(LOCAL)
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* PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE)
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*********************************************************************************/
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I2OSTATUS I2OMsgDisable( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned char n ) /* b'1' - msg 0
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* b'10'- msg 1
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* b'11'- both
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*/
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{
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unsigned int reg, val;
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if ( ( n & 0x3 ) == 0 )
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{
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/* neither msg 0, nor msg 1 */
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return I2OMSGINVALID;
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}
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/* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base
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* LOCAL : disable local inbound message interrupt, eumbbar as base
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*/
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reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
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val = load_runtime_reg( base, reg );
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val &= 0xfffffffc; /* masked out the msg interrupt bits */
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val |= ( n & 0x3 );
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store_runtime_reg( base, reg, val );
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return I2OSUCCESS;
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}
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/**************************************************************************
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* function: I2OMsgGet
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*
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* description: Local processor reads the nth Msg register from its inbound msg,
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* or a PCI Master reads nth outbound msg from device
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*
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* return I2OSUCCESS if no error, otherwise return I2OMSGINVALID.
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*
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* note:
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* If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed.
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* If it is remote, outbound msg on the device is read; otherwise local inbound msg is read
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*************************************************************************/
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I2OSTATUS I2OMsgGet ( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /*pcsrbar/eumbbar */
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unsigned int n, /* 0 or 1 */
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unsigned int *msg )
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{
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if ( n >= I2O_NUM_MSG || msg == 0 )
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{
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return I2OMSGINVALID;
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}
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if ( loc == REMOTE )
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{
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/* read the outbound msg of the device, pcsrbar as base */
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*msg = load_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET );
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}
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else
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{
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/* read the inbound msg sent by PCI master, eumbbar as base */
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*msg = load_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET );
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}
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return I2OSUCCESS;
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}
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/***************************************************************
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* function: I2OMsgPost
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*
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* description: Kahlua writes to its nth outbound msg register
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* PCI master writes to nth inbound msg register of device
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*
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* return I2OSUCCESS if no error, otherwise return I2OMSGINVALID.
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*
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* note:
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* If it is not local, pcsrbar must be passed to the function. Otherwise eumbbar is passed.
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*
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* If it is remote, inbound msg on the device is written; otherwise local outbound msg is written
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***************************************************************/
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I2OSTATUS I2OMsgPost( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /*pcsrbar/eumbbar */
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unsigned int n, /* 0 or 1 */
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unsigned int msg )
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{
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if ( n >= I2O_NUM_MSG )
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{
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return I2OMSGINVALID;
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}
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if ( loc == REMOTE )
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{
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/* write to the inbound msg register of the device, pcsrbar as base */
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store_runtime_reg( base, I2O_IMR0+n*I2O_REG_OFFSET, msg );
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}
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else
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{
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/* write to the outbound msg register for PCI master to read, eumbbar as base */
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store_runtime_reg( base, I2O_OMR0+n*I2O_REG_OFFSET, msg );
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}
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return I2OSUCCESS;
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}
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/***********************************************************************
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* function: I2ODBEnable
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*
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* description: Local processor enables it's inbound doorbell interrupt
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* PCI master enables outbound doorbell interrupt of devices
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* Other previously enabled interrupts are preserved.
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* Return I2OSUCCESS if no error otherwise return I2ODBINVALID
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*
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* note:
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* In DoorBell interrupt is generated by PCI master and serviced by local processor
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* Out Doorbell interrupt is generated by local processor and serviced by PCI master
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*
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* Out Doorbell interrupt is generated by local processor and serviced by PCI master
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* PCI master needs to enable the outbound doorbell interrupts of device it wants to handle
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**********************************************************************/
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I2OSTATUS I2ODBEnable( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
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{
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/* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device
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* LOCAL : Kahlua initializes its inbound doorbell message
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*/
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unsigned int val;
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if ( loc == LOCAL && ( in_db & 0x3 ) == 0 )
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{
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return I2ODBINVALID;
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}
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if ( loc == REMOTE )
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{
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/* pcsrbar is base */
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val = load_runtime_reg( base, I2O_OMIMR );
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val &= 0xfffffff7;
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store_runtime_reg( base, I2O_OMIMR , val );
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}
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else
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{
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/* eumbbar is base */
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val = load_runtime_reg( base, I2O_IMIMR);
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in_db = ( (~in_db) & 0x3 ) << 3;
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val = ( val & 0xffffffe7) | in_db;
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store_runtime_reg( base, I2O_IMIMR, val );
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}
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return I2OSUCCESS;
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}
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/**********************************************************************************
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* function: I2ODBDisable
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*
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* description: local processor disables its inbound DoorBell Interrupt
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* PCI master disables outbound DoorBell interrupt of device
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* Other previously enabled interrupts are preserved.
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* return I2OSUCCESS if no error.Otherwise return I2ODBINVALID
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*
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* note:
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* local processor needs to disable its inbound doorbell interrupts it is not interested
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*
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* PCI master needs to disable outbound doorbell interrupts of device it is not interested
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************************************************************************************/
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I2OSTATUS I2ODBDisable( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
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{
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/* LOCATION - REMOTE : handle device's out bound message initialization
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* LOCAL : handle local in bound message initialization
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*/
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unsigned int val;
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if ( loc == LOCAL && ( in_db & 0x3 ) == 0 )
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{
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return I2ODBINVALID;
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}
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if ( loc == REMOTE )
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{
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/* pcsrbar is the base */
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val = load_runtime_reg( base, I2O_OMIMR );
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val |= 0x8;
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store_runtime_reg( base, I2O_OMIMR, val );
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}
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else
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{
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val = load_runtime_reg( base, I2O_IMIMR);
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in_db = ( in_db & 0x3 ) << 3;
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val |= in_db;
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store_runtime_reg( base, I2O_IMIMR, val );
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}
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return I2OSUCCESS;
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}
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/**********************************************************************************
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* function: I2ODBGet
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*
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* description: Local processor reads its in doorbell register,
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* PCI master reads the outdoorbell register of device.
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* After a doorbell register is read, the whole register will be cleared.
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* Otherwise, HW keeps generating interrupt.
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*
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* note:
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* If it is not local, pcsrbar must be passed to the function.
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* Otherwise eumbbar is passed.
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*
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* If it is remote, out doorbell register on the device is read.
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* Otherwise local in doorbell is read
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*
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* If the register is not cleared by write to it, any remaining bit of b'1's
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* will cause interrupt pending.
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*********************************************************************************/
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unsigned int I2ODBGet( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base) /* pcsrbar/eumbbar */
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{
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unsigned int msg, val;
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if ( loc == REMOTE )
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{
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/* read outbound doorbell register of device, pcsrbar is the base */
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val = load_runtime_reg( base, I2O_ODBR );
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msg = val & 0xe0000000;
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store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */
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}
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else
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{
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/* read the inbound doorbell register, eumbbar is the base */
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val = load_runtime_reg( base, I2O_IDBR );
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store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */
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msg = val;
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}
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return msg;
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}
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/**********************************************************************
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* function: I2ODBPost
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*
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* description: local processor writes to a outbound doorbell register,
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* PCI master writes to the inbound doorbell register of device
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*
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* note:
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* If it is not local, pcsrbar must be passed to the function.
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* Otherwise eumbbar is passed.
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*
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* If it is remote, in doorbell register on the device is written.
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* Otherwise local out doorbell is written
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*********************************************************************/
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void I2ODBPost( LOCATION loc, /* REMOTE/LOCAL */
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unsigned int base, /* pcsrbar/eumbbar */
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unsigned int msg ) /* in / out */
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{
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if ( loc == REMOTE )
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{
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/* write to inbound doorbell register of device, pcsrbar is the base */
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store_runtime_reg( base, I2O_IDBR, msg );
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}
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else
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{
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/* write to local outbound doorbell register, eumbbar is the base */
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store_runtime_reg( base, I2O_ODBR, msg & 0x1fffffff );
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}
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}
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/********************************************************************
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* function: I2OOutMsgStatGet
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*
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* description: PCI master reads device's outbound msg unit interrupt status.
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* Reading an interrupt status register,
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* the register will be cleared.
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*
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* The value of the status register is AND with the outbound
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* interrupt mask and result is returned.
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*
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* note:
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* pcsrbar must be passed to the function.
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********************************************************************/
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I2OSTATUS I2OOutMsgStatGet( unsigned int pcsrbar, I2OOMSTAT *val )
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{
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unsigned int stat;
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unsigned int mask;
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if ( val == 0 )
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{
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return I2OINVALID;
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}
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/* read device's outbound status */
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stat = load_runtime_reg( pcsrbar, I2O_OMISR );
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mask = load_runtime_reg( pcsrbar, I2O_OMIMR );
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store_runtime_reg( pcsrbar, I2O_OMISR, stat & 0xffffffd7);
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stat &= mask;
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val->rsvd0 = ( stat & 0xffffffc0 ) >> 6;
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val->opqi = ( stat & 0x00000020 ) >> 5;
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val->rsvd1 = ( stat & 0x00000010 ) >> 4;
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val->odi = ( stat & 0x00000008 ) >> 3;
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val->rsvd2 = ( stat & 0x00000004 ) >> 2;
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val->om1i = ( stat & 0x00000002 ) >> 1;
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val->om0i = ( stat & 0x00000001 );
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return I2OSUCCESS;
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}
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/********************************************************************
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* function: I2OInMsgStatGet
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*
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* description: Local processor reads its inbound msg unit interrupt status.
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* Reading an interrupt status register,
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* the register will be cleared.
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*
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* The inbound msg interrupt status is AND with the inbound
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* msg interrupt mask and result is returned.
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*
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* note:
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* eumbbar must be passed to the function.
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********************************************************************/
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I2OSTATUS I2OInMsgStatGet(unsigned int eumbbar, I2OIMSTAT *val)
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{
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unsigned int stat;
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unsigned int mask;
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if ( val == 0 )
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{
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return I2OINVALID;
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}
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/* read device's outbound status */
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stat = load_runtime_reg( eumbbar, I2O_OMISR );
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mask = load_runtime_reg( eumbbar, I2O_OMIMR );
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store_runtime_reg( eumbbar, I2O_OMISR, stat & 0xffffffe7 );
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stat &= mask;
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val->rsvd0 = ( stat & 0xfffffe00 ) >> 9;
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val->ofoi = ( stat & 0x00000100 ) >> 8;
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val->ipoi = ( stat & 0x00000080 ) >> 7;
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val->rsvd1 = ( stat & 0x00000040 ) >> 6;
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val->ipqi = ( stat & 0x00000020 ) >> 5;
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val->mci = ( stat & 0x00000010 ) >> 4;
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val->idi = ( stat & 0x00000008 ) >> 3;
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val->rsvd2 = ( stat & 0x00000004 ) >> 2;
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val->im1i = ( stat & 0x00000002 ) >> 1;
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val->im0i = ( stat & 0x00000001 );
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return I2OSUCCESS;
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}
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/***********************************************************
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* function: I2OFIFOInit
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*
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* description: Configure the I2O FIFO, including QBAR,
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* IFHPR/IFTPR, IPHPR/IPTPR, OFHPR/OFTPR,
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* OPHPR/OPTPR, MUCR.
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*
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* return I2OSUCCESS if no error,
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* otherwise return I2OQUEINVALID
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*
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* note: It is NOT this driver's responsibility of initializing
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* MFA blocks, i.e., FIFO queue itself. The MFA blocks
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* must be initialized before I2O unit can be used.
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***********************************************************/
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I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
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QUEUE_SIZE sz, /* value of CQS of MUCR */
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unsigned int qba) /* queue base address that must be aligned at 1M */
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{
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if ( ( qba & 0xfffff ) != 0 )
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{
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/* QBA must be aligned at 1Mbyte boundary */
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return I2OQUEINVALID;
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}
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store_runtime_reg( eumbbar, I2O_QBAR, qba );
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store_runtime_reg( eumbbar, I2O_MUCR, (unsigned int)sz );
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store_runtime_reg( eumbbar, I2O_IFHPR, qba );
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store_runtime_reg( eumbbar, I2O_IFTPR, qba );
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store_runtime_reg( eumbbar, I2O_IPHPR, qba + 1 * ( sz << 11 ));
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store_runtime_reg( eumbbar, I2O_IPTPR, qba + 1 * ( sz << 11 ));
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store_runtime_reg( eumbbar, I2O_OFHPR, qba + 2 * ( sz << 11 ));
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store_runtime_reg( eumbbar, I2O_OFTPR, qba + 2 * ( sz << 11 ));
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store_runtime_reg( eumbbar, I2O_OPHPR, qba + 3 * ( sz << 11 ));
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store_runtime_reg( eumbbar, I2O_OPTPR, qba + 3 * ( sz << 11 ));
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fifo_stat.qsz = sz;
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fifo_stat.qba = qba;
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return I2OSUCCESS;
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}
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|
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/**************************************************
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* function: I2OFIFOEnable
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*
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* description: Enable the circular queue
|
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* return I2OSUCCESS if no error.
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* Otherwise I2OQUEINVALID is returned.
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*
|
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* note:
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*************************************************/
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I2OSTATUS I2OFIFOEnable( unsigned int eumbbar )
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{
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unsigned int val;
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if ( fifo_stat.qba == 0xfffffff )
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{
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return I2OQUEINVALID;
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}
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val = load_runtime_reg( eumbbar, I2O_MUCR );
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store_runtime_reg( eumbbar, I2O_MUCR, val | 0x1 );
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return I2OSUCCESS;
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}
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|
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/**************************************************
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* function: I2OFIFODisable
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*
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* description: Disable the circular queue
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*
|
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* note:
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*************************************************/
|
|
void I2OFIFODisable( unsigned int eumbbar )
|
|
{
|
|
if ( fifo_stat.qba == 0xffffffff )
|
|
{
|
|
/* not enabled */
|
|
return;
|
|
}
|
|
|
|
unsigned int val = load_runtime_reg( eumbbar, I2O_MUCR );
|
|
store_runtime_reg( eumbbar, I2O_MUCR, val & 0xfffffffe );
|
|
}
|
|
|
|
/****************************************************
|
|
* function: I2OFIFOAlloc
|
|
*
|
|
* description: Allocate a free MFA from free FIFO.
|
|
* return I2OSUCCESS if no error.
|
|
* return I2OQUEEMPTY if no more free MFA.
|
|
* return I2OINVALID on other errors.
|
|
*
|
|
* A free MFA must be allocated before a
|
|
* message can be posted.
|
|
*
|
|
* note:
|
|
* PCI Master allocates a free MFA from inbound queue of device
|
|
* (pcsrbar is the base,) through the inbound queue port of device
|
|
* while local processor allocates a free MFA from its outbound
|
|
* queue (eumbbar is the base.)
|
|
*
|
|
****************************************************/
|
|
I2OSTATUS I2OFIFOAlloc( LOCATION loc,
|
|
unsigned int base,
|
|
void **pMsg )
|
|
{
|
|
I2OSTATUS stat = I2OSUCCESS;
|
|
void *pHdr, *pTil;
|
|
|
|
if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff )
|
|
{
|
|
/* not configured */
|
|
return I2OQUEINVALID;
|
|
}
|
|
|
|
if ( loc == REMOTE )
|
|
{
|
|
/* pcsrbar is the base and read the inbound free tail ptr */
|
|
pTil = (void *)load_runtime_reg( base, I2O_IFQPR );
|
|
if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
|
|
{
|
|
stat = I2OQUEEMPTY;
|
|
}
|
|
else
|
|
{
|
|
*pMsg = pTil;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* eumbbar is the base and read the outbound free tail ptr */
|
|
pHdr = (void *)load_runtime_reg( base, I2O_OFHPR ); /* queue head */
|
|
pTil = (void *)load_runtime_reg( base, I2O_OFTPR ); /* queue tail */
|
|
|
|
/* check underflow */
|
|
if ( pHdr == pTil )
|
|
{
|
|
/* hdr and til point to the same fifo item, no free MFA */
|
|
stat = I2OQUEEMPTY;
|
|
}
|
|
else
|
|
{
|
|
/* update OFTPR */
|
|
*pMsg = (void *)(*(unsigned char *)pTil);
|
|
pTil = (void *)((unsigned int)pTil + 4);
|
|
if ( (unsigned int)pTil == fifo_stat.qba + ( 4 * ( fifo_stat.qsz << 11 ) ) )
|
|
{
|
|
/* reach the upper limit */
|
|
pTil = (void *)(fifo_stat.qba + ( 3 * (fifo_stat.qsz << 11) ));
|
|
}
|
|
store_runtime_reg( base, I2O_OFTPR, (unsigned int)pTil );
|
|
}
|
|
}
|
|
|
|
return stat;
|
|
}
|
|
|
|
/******************************************************
|
|
* function: I2OFIFOFree
|
|
*
|
|
* description: Free a used MFA back to free queue after
|
|
* use.
|
|
* return I2OSUCCESS if no error.
|
|
* return I2OQUEFULL if inbound free queue
|
|
* overflow
|
|
*
|
|
* note: PCI Master frees a MFA into device's outbound queue
|
|
* (OFQPR) while local processor frees a MFA into its
|
|
* inbound queue (IFHPR).
|
|
*****************************************************/
|
|
I2OSTATUS I2OFIFOFree( LOCATION loc,
|
|
unsigned int base,
|
|
void *pMsg )
|
|
{
|
|
void **pHdr, **pTil;
|
|
I2OSTATUS stat = I2OSUCCESS;
|
|
|
|
if ( fifo_stat.qba == 0xffffffff || pMsg == 0 )
|
|
{
|
|
return I2OQUEINVALID;
|
|
}
|
|
|
|
if ( loc == REMOTE )
|
|
{
|
|
/* pcsrbar is the base */
|
|
store_runtime_reg( base, I2O_OFQPR, (unsigned int)pMsg );
|
|
}
|
|
else
|
|
{
|
|
/* eumbbar is the base */
|
|
pHdr = (void **)load_runtime_reg( base, I2O_IFHPR );
|
|
pTil = (void **)load_runtime_reg( base, I2O_IFTPR );
|
|
|
|
/* store MFA */
|
|
*pHdr = pMsg;
|
|
|
|
/* update IFHPR */
|
|
pHdr += 4;
|
|
|
|
if ( (unsigned int)pHdr == fifo_stat.qba + ( fifo_stat.qsz << 11 ) )
|
|
{
|
|
/* reach the upper limit */
|
|
pHdr = (void **)fifo_stat.qba;
|
|
}
|
|
|
|
/* check inbound free queue overflow */
|
|
if ( pHdr != pTil )
|
|
{
|
|
store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
|
|
}
|
|
else
|
|
{
|
|
stat = I2OQUEFULL;
|
|
}
|
|
|
|
}
|
|
|
|
return stat;
|
|
|
|
}
|
|
|
|
/*********************************************
|
|
* function: I2OFIFOPost
|
|
*
|
|
* description: Post a msg into FIFO post queue
|
|
* the value of msg must be the one
|
|
* returned by I2OFIFOAlloc
|
|
*
|
|
* note: PCI Master posts a msg into device's inbound queue
|
|
* (IFQPR) while local processor post a msg into device's
|
|
* outbound queue (OPHPR)
|
|
*********************************************/
|
|
I2OSTATUS I2OFIFOPost( LOCATION loc,
|
|
unsigned int base,
|
|
void *pMsg )
|
|
{
|
|
void **pHdr, **pTil;
|
|
I2OSTATUS stat = I2OSUCCESS;
|
|
|
|
if ( fifo_stat.qba == 0xffffffff || pMsg == 0 )
|
|
{
|
|
return I2OQUEINVALID;
|
|
}
|
|
|
|
if ( loc == REMOTE )
|
|
{
|
|
/* pcsrbar is the base */
|
|
store_runtime_reg( base, I2O_IFQPR, (unsigned int)pMsg );
|
|
}
|
|
else
|
|
{
|
|
/* eumbbar is the base */
|
|
pHdr = (void **)load_runtime_reg( base, I2O_OPHPR );
|
|
pTil = (void **)load_runtime_reg( base, I2O_OPTPR );
|
|
|
|
/* store MFA */
|
|
*pHdr = pMsg;
|
|
|
|
/* update IFHPR */
|
|
pHdr += 4;
|
|
|
|
if ( (unsigned int)pHdr == fifo_stat.qba + 3 * ( fifo_stat.qsz << 11 ) )
|
|
{
|
|
/* reach the upper limit */
|
|
pHdr = (void **)(fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) );
|
|
}
|
|
|
|
/* check post queue overflow */
|
|
if ( pHdr != pTil )
|
|
{
|
|
store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
|
|
}
|
|
else
|
|
{
|
|
stat = I2OQUEFULL;
|
|
}
|
|
}
|
|
|
|
return stat;
|
|
}
|
|
|
|
/************************************************
|
|
* function: I2OFIFOGet
|
|
*
|
|
* description: Read a msg from FIFO
|
|
* This function should be called
|
|
* only when there is a corresponding
|
|
* msg interrupt.
|
|
*
|
|
* note: PCI Master reads a msg from device's outbound queue
|
|
* (OFQPR) while local processor reads a msg from device's
|
|
* inbound queue (IPTPR)
|
|
************************************************/
|
|
I2OSTATUS I2OFIFOGet( LOCATION loc,
|
|
unsigned int base,
|
|
void **pMsg )
|
|
{
|
|
I2OSTATUS stat = I2OSUCCESS;
|
|
void *pHdr, *pTil;
|
|
|
|
if ( pMsg == 0 || *pMsg == 0 || fifo_stat.qba == 0xffffffff )
|
|
{
|
|
/* not configured */
|
|
return I2OQUEINVALID;
|
|
}
|
|
|
|
if ( loc == REMOTE )
|
|
{
|
|
/* pcsrbar is the base */
|
|
pTil = (void *)load_runtime_reg( base, I2O_OFQPR );
|
|
if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
|
|
{
|
|
stat = I2OQUEEMPTY;
|
|
}
|
|
else
|
|
{
|
|
*pMsg = pTil;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* eumbbar is the base and read the outbound free tail ptr */
|
|
pHdr = (void *)load_runtime_reg( base, I2O_IPHPR ); /* queue head */
|
|
pTil = (void *)load_runtime_reg( base, I2O_IPTPR ); /* queue tail */
|
|
|
|
/* check underflow */
|
|
if ( pHdr == pTil )
|
|
{
|
|
/* no free MFA */
|
|
stat = I2OQUEEMPTY;
|
|
}
|
|
else
|
|
{
|
|
/* update OFTPR */
|
|
*pMsg = (void *)(*(unsigned char *)pTil);
|
|
pTil = (void *)((unsigned int)pTil + 4);
|
|
if ( (unsigned int)pTil == fifo_stat.qba + 2 * ( fifo_stat.qsz << 11 ) )
|
|
{
|
|
/* reach the upper limit */
|
|
pTil = (void *)(fifo_stat.qba + 1 * (fifo_stat.qsz << 11) );
|
|
}
|
|
|
|
store_runtime_reg( base, I2O_IPTPR, (unsigned int)pTil );
|
|
}
|
|
}
|
|
|
|
return stat;
|
|
}
|
|
|
|
/********************************************************
|
|
* function: I2OIOP
|
|
*
|
|
* description: Get the I2O PCI configuration identification
|
|
* register.
|
|
*
|
|
* note: PCI master should pass pcsrbar while local processor
|
|
* should pass eumbbar.
|
|
*********************************************************/
|
|
I2OSTATUS I2OPCIConfigGet( LOCATION loc,
|
|
unsigned int base,
|
|
I2OIOP * val)
|
|
{
|
|
unsigned int tmp;
|
|
if ( val == 0 )
|
|
{
|
|
return I2OINVALID;
|
|
}
|
|
tmp = load_runtime_reg( base, PCI_CFG_CLA );
|
|
val->base_class = ( tmp & 0xFF) << 16;
|
|
tmp = load_runtime_reg( base, PCI_CFG_SCL );
|
|
val->sub_class= ( (tmp & 0xFF) << 8 );
|
|
tmp = load_runtime_reg( base, PCI_CFG_PIC );
|
|
val->prg_code = (tmp & 0xFF);
|
|
return I2OSUCCESS;
|
|
}
|
|
|
|
/*********************************************************
|
|
* function: I2OFIFOIntEnable
|
|
*
|
|
* description: Enable the circular post queue interrupt
|
|
*
|
|
* note:
|
|
* PCI master enables outbound FIFO interrupt of device
|
|
* pscrbar is the base
|
|
* Device enables its inbound FIFO interrupt
|
|
* eumbbar is the base
|
|
*******************************************************/
|
|
void I2OFIFOIntEnable( LOCATION loc, unsigned int base )
|
|
{
|
|
unsigned int reg, val;
|
|
|
|
/* LOCATION - REMOTE : enable outbound message of device, pcsrbar as base
|
|
* LOCAL : enable local inbound message, eumbbar as base
|
|
*/
|
|
reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
|
|
val = load_runtime_reg( base, reg );
|
|
|
|
val &= 0xffffffdf; /* clear the msg interrupt bits */
|
|
store_runtime_reg( base, reg, val );
|
|
|
|
}
|
|
|
|
/****************************************************
|
|
* function: I2OFIFOIntDisable
|
|
*
|
|
* description: Disable the circular post queue interrupt
|
|
*
|
|
* note:
|
|
* PCI master disables outbound FIFO interrupt of device
|
|
* (pscrbar is the base)
|
|
* Device disables its inbound FIFO interrupt
|
|
* (eumbbar is the base)
|
|
*****************************************************/
|
|
void I2OFIFOIntDisable( LOCATION loc, unsigned int base )
|
|
{
|
|
|
|
/* LOCATION - REMOTE : disable outbound message interrupt of device, pcsrbar as base
|
|
* LOCAL : disable local inbound message interrupt, eumbbar as base
|
|
*/
|
|
unsigned int reg = ( loc == REMOTE ? I2O_OMIMR : I2O_IMIMR );
|
|
unsigned int val = load_runtime_reg( base, reg );
|
|
|
|
val |= 0x00000020; /* masked out the msg interrupt bits */
|
|
store_runtime_reg( base, reg, val );
|
|
|
|
}
|
|
|
|
/*********************************************************
|
|
* function: I2OFIFOOverflowIntEnable
|
|
*
|
|
* description: Enable the circular queue overflow interrupt
|
|
*
|
|
* note:
|
|
* Device enables its inbound FIFO post overflow interrupt
|
|
* and outbound free overflow interrupt.
|
|
* eumbbar is the base
|
|
*******************************************************/
|
|
void I2OFIFOOverflowIntEnable( unsigned int eumbbar )
|
|
{
|
|
unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR );
|
|
|
|
val &= 0xfffffe7f; /* clear the two overflow interrupt bits */
|
|
store_runtime_reg( eumbbar, I2O_IMIMR, val );
|
|
|
|
}
|
|
|
|
/****************************************************
|
|
* function: I2OFIFOOverflowIntDisable
|
|
*
|
|
* description: Disable the circular queue overflow interrupt
|
|
*
|
|
* note:
|
|
* Device disables its inbound post FIFO overflow interrupt
|
|
* and outbound free FIFO overflow interrupt
|
|
* (eumbbar is the base)
|
|
*****************************************************/
|
|
void I2OFIFOOverflowIntDisable( unsigned int eumbbar )
|
|
{
|
|
|
|
unsigned int val = load_runtime_reg( eumbbar, I2O_IMIMR );
|
|
|
|
val |= 0x00000180; /* masked out the msg overflow interrupt bits */
|
|
store_runtime_reg( eumbbar, I2O_IMIMR, val );
|
|
}
|