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6e31c62a17
add DM/DTS support for the UEC ethernet on QUICC Engine
Block.
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com>
Series-changes: 3
- revert:
commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled")
as now qe works with DM and DM_ETH support.
- fix mailaddress from Holger
Series-changes: 2
- add comments from Qiang Zhao:
- add device node documentation
- I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c
because using drivers/net/fsl_mdio.c leads in none existent
udevice mdio@3320
instead boards with DM ETH support should use now this
driver.
- remove RFC tag
Commit-notes:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This Code should be removed if all boards are converted
to DM/DTS.
- add the DM based qe uec driver under drivers/net/qe
- Therefore copied the files uccf.c uccf.h uec.h from
drivers/qe. So there are a lot of Codingstyle problems
currently. I fix them in next version if this RFC
patch is OK or it needs some changes.
- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c
Used a lot of functions from drivers/qe/uec.c
- seperated the PHY specific code into seperate file
drivers/net/qe/dm_qe_uec_phy.c
END
53 lines
2.3 KiB
Text
53 lines
2.3 KiB
Text
* UCC (Unified Communications Controllers)
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Required properties:
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- compatible : ucc_geth
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- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
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- reg : Offset and length of the register set for the device
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- rx-clock-name: the UCC receive clock source
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"none": clock source is disabled
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"brg1" through "brg16": clock source is BRG1-BRG16, respectively
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"clk1" through "clk24": clock source is CLK1-CLK24, respectively
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- tx-clock-name: the UCC transmit clock source
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"none": clock source is disabled
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"brg1" through "brg16": clock source is BRG1-BRG16, respectively
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"clk1" through "clk24": clock source is CLK1-CLK24, respectively
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The following two properties are deprecated. rx-clock has been replaced
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with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
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Drivers that currently use the deprecated properties should continue to
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do so, in order to support older device trees, but they should be updated
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to check for the new properties first.
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- rx-clock : represents the UCC receive clock source.
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0x00 : clock source is disabled;
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0x1~0x10 : clock source is BRG1~BRG16 respectively;
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0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
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- tx-clock: represents the UCC transmit clock source;
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0x00 : clock source is disabled;
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0x1~0x10 : clock source is BRG1~BRG16 respectively;
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0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
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- phy-handle : The phandle for the PHY connected to this controller.
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- phy-connection-type : a string naming the controller/PHY interface type,
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i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
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Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
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"tbi", or "rtbi".
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- pio-handle : The phandle for the Parallel I/O port configuration.
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Deprecated properties:
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- device-id : the ucc number(1-8), corresponding to UCCx in UM.
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you should use cell-index
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Example:
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ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <1>;
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reg = <2000 200>;
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interrupts = <a0 0>;
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interrupt-parent = <700>;
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mac-address = [ 00 04 9f 00 23 23 ];
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rx-clock = "none";
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tx-clock = "clk9";
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phy-handle = <212000>;
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phy-connection-type = "gmii";
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pio-handle = <140001>;
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};
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