mirror of
https://github.com/AsahiLinux/u-boot
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323d1f9d5b
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
203 lines
4.4 KiB
C
203 lines
4.4 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/init.h>
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#include <mach/sc-regs.h>
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#include <mach/sg-regs.h>
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#undef DPLL_SSC_RATE_1PER
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static int dpll_init(unsigned int dram_freq)
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{
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u32 tmp;
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/*
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* Set Frequency
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* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
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* to FOUT (DPLLCTRL.bit[29:20])
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*/
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tmp = readl(SC_DPLLCTRL);
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tmp &= ~0x000f0000;
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switch (dram_freq) {
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case 1333:
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tmp |= 0x000d0000;
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break;
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case 1600:
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tmp |= 0x000c0000;
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break;
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default:
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pr_err("Unsupported frequency");
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return -EINVAL;
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}
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#if defined(DPLL_SSC_RATE_1PER)
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tmp &= ~SC_DPLLCTRL_SSC_RATE;
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#else
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tmp |= SC_DPLLCTRL_SSC_RATE;
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#endif
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writel(tmp, SC_DPLLCTRL);
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tmp = readl(SC_DPLLCTRL2);
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tmp |= SC_DPLLCTRL2_NRSTDS;
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writel(tmp, SC_DPLLCTRL2);
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return 0;
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}
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static void upll_init(void)
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{
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u32 tmp, clk_mode_upll, clk_mode_axosel;
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tmp = readl(SG_PINMON0);
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clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
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tmp = readl(SC_UPLLCTRL);
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tmp &= ~0x18000000;
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writel(tmp, SC_UPLLCTRL);
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if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
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/* AXO: 25MHz */
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tmp &= ~0x07ffffff;
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tmp |= 0x0228f5c0;
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} else {
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/* AXO: default 24.576MHz */
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tmp &= ~0x07ffffff;
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tmp |= 0x02328000;
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}
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}
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writel(tmp, SC_UPLLCTRL);
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/* set 1 to K_LD(UPLLCTRL.bit[27]) */
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tmp |= 0x08000000;
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writel(tmp, SC_UPLLCTRL);
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/* wait 10 usec */
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udelay(10);
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/* set 1 to SNRT(UPLLCTRL.bit[28]) */
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tmp |= 0x10000000;
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writel(tmp, SC_UPLLCTRL);
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}
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static void vpll_init(void)
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{
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u32 tmp, clk_mode_axosel;
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tmp = readl(SG_PINMON0);
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* set 1 to VPLA27WP and VPLA27WP */
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tmp = readl(SC_VPLL27ACTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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/* Set 0 to VPLA_K_LD and VPLB_K_LD */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Set 0 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27BCTRL2);
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
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/* AXO: 25MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066664;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066664;
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writel(tmp, SC_VPLL27BCTRL3);
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} else {
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/* AXO: default 24.576MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27BCTRL3);
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}
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/* Set 1 to VPLA_K_LD and VPLB_K_LD */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* wait 10 usec */
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udelay(10);
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/* Set 0 to VPLA_SNRST and VPLB_SNRST */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* set 0 to VPLA27WP and VPLA27WP */
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tmp = readl(SC_VPLL27ACTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= ~0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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}
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int ph1_ld4_pll_init(const struct uniphier_board_data *bd)
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{
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int ret;
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ret = dpll_init(bd->dram_freq);
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if (ret)
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return ret;
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upll_init();
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vpll_init();
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/*
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* Wait 500 usec until dpll get stable
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* We wait 10 usec in upll_init() and vpll_init()
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* so 20 usec can be saved here.
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*/
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udelay(480);
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return 0;
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}
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