mirror of
https://github.com/AsahiLinux/u-boot
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323d1f9d5b
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
139 lines
2.6 KiB
C
139 lines
2.6 KiB
C
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <mach/ddrphy-regs.h>
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void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
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{
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int dx;
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u32 __iomem tmp, *p;
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for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
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p = &phy->dx[dx].gcr;
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tmp = readl(p);
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/* Specify the rank that should be write leveled */
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tmp &= ~DXGCR_WLRKEN_MASK;
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tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
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writel(tmp, p);
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}
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p = &phy->dtcr;
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tmp = readl(p);
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/* Specify the rank used during data bit deskew and eye centering */
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tmp &= ~DTCR_DTRANK_MASK;
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tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
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/* Use Multi-Purpose Register for DQS gate training */
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tmp |= DTCR_DTMPR;
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/* Specify the rank enabled for data-training */
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tmp &= ~DTCR_RNKEN_MASK;
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tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
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writel(tmp, p);
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}
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struct ddrphy_init_sequence {
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char *description;
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u32 init_flag;
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u32 done_flag;
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u32 err_flag;
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};
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static struct ddrphy_init_sequence init_sequence[] = {
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{
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"DRAM Initialization",
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PIR_DRAMRST | PIR_DRAMINIT,
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PGSR0_DIDONE,
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PGSR0_DIERR
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},
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{
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"Write Leveling",
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PIR_WL,
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PGSR0_WLDONE,
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PGSR0_WLERR
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},
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{
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"Read DQS Gate Training",
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PIR_QSGATE,
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PGSR0_QSGDONE,
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PGSR0_QSGERR
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},
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{
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"Write Leveling Adjustment",
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PIR_WLADJ,
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PGSR0_WLADONE,
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PGSR0_WLAERR
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},
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{
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"Read Bit Deskew",
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PIR_RDDSKW,
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PGSR0_RDDONE,
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PGSR0_RDERR
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},
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{
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"Write Bit Deskew",
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PIR_WRDSKW,
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PGSR0_WDDONE,
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PGSR0_WDERR
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},
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{
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"Read Eye Training",
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PIR_RDEYE,
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PGSR0_REDONE,
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PGSR0_REERR
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},
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{
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"Write Eye Training",
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PIR_WREYE,
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PGSR0_WEDONE,
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PGSR0_WEERR
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}
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};
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int ddrphy_training(struct ddrphy __iomem *phy)
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{
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int i;
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u32 pgsr0;
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u32 init_flag = PIR_INIT;
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u32 done_flag = PGSR0_IDONE;
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int timeout = 50000; /* 50 msec is long enough */
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#ifdef DISPLAY_ELAPSED_TIME
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ulong start = get_timer(0);
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#endif
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for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
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init_flag |= init_sequence[i].init_flag;
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done_flag |= init_sequence[i].done_flag;
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}
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writel(init_flag, &phy->pir);
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do {
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if (--timeout < 0) {
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printf("%s: error: timeout during DDR training\n",
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__func__);
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return -1;
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}
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udelay(1);
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pgsr0 = readl(&phy->pgsr[0]);
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} while ((pgsr0 & done_flag) != done_flag);
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for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
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if (pgsr0 & init_sequence[i].err_flag) {
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printf("%s: error: %s failed\n", __func__,
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init_sequence[i].description);
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return -1;
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}
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}
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#ifdef DISPLAY_ELAPSED_TIME
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printf("%s: info: elapsed time %ld msec\n", get_timer(start));
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#endif
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return 0;
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}
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