mirror of
https://github.com/AsahiLinux/u-boot
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323d1f9d5b
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled. Each SoC has its own defconfig file
for the build-test coverage. Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.
Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture. In fact, some
SoCs of UniPhier family are very similar:
- PH1-LD4 and PH1-sLD8
- PH1-LD6b and ProXstream2 (will be added in the upcoming commit)
This commit will be helpful to merge some defconfig files for better
maintainability.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <mach/ddrphy-regs.h>
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int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
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{
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u32 tmp;
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writel(0x0300c473, &phy->pgcr[1]);
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if (freq == 1333) {
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writel(0x0a806844, &phy->ptr[0]);
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writel(0x208e0124, &phy->ptr[1]);
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} else {
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writel(0x0c807d04, &phy->ptr[0]);
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writel(0x2710015E, &phy->ptr[1]);
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}
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writel(0x00083DEF, &phy->ptr[2]);
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if (freq == 1333) {
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writel(0x0f051616, &phy->ptr[3]);
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writel(0x06ae08d6, &phy->ptr[4]);
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} else {
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writel(0x12061A80, &phy->ptr[3]);
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writel(0x08027100, &phy->ptr[4]);
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}
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writel(0xF004001A, &phy->dsgcr);
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/* change the value of the on-die pull-up/pull-down registors */
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tmp = readl(&phy->dxccr);
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tmp &= ~0x0ee0;
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tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
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writel(tmp, &phy->dxccr);
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writel(0x0000040B, &phy->dcr);
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if (freq == 1333) {
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writel(0x85589955, &phy->dtpr[0]);
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if (size == 1)
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writel(0x1a8253c0, &phy->dtpr[1]);
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else
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writel(0x1a8363c0, &phy->dtpr[1]);
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writel(0x5002c200, &phy->dtpr[2]);
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writel(0x00000b51, &phy->mr0);
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} else {
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writel(0x999cbb66, &phy->dtpr[0]);
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if (size == 1)
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writel(0x1a82dbc0, &phy->dtpr[1]);
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else
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writel(0x1a878400, &phy->dtpr[1]);
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writel(0xa00214f8, &phy->dtpr[2]);
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writel(0x00000d71, &phy->mr0);
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}
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writel(0x00000006, &phy->mr1);
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if (freq == 1333)
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writel(0x00000290, &phy->mr2);
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else
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writel(0x00000298, &phy->mr2);
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writel(0x00000800, &phy->mr3);
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while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
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;
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writel(0x0300C473, &phy->pgcr[1]);
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writel(0x0000005D, &phy->zq[0].cr[1]);
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return 0;
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}
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