mirror of
https://github.com/AsahiLinux/u-boot
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5e112c7ca8
Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the status of device node is "okay", initr_watchdog will be called and finally calls ulp_wdt_probe() and ulp_wdt_start(). Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de>
224 lines
4.9 KiB
C
224 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <dm.h>
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#include <wdt.h>
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/*
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* MX7ULP WDOG Register Map
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*/
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struct wdog_regs {
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u32 cs;
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u32 cnt;
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u32 toval;
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u32 win;
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};
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struct ulp_wdt_priv {
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struct wdog_regs *wdog;
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u32 clk_rate;
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};
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
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#endif
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#define REFRESH_WORD0 0xA602 /* 1st refresh word */
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#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
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#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
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#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
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#define UNLOCK_WORD 0xD928C520 /* unlock word */
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#define REFRESH_WORD 0xB480A602 /* refresh word */
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#define WDGCS_WDGE BIT(7)
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#define WDGCS_WDGUPDATE BIT(5)
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#define WDGCS_RCS BIT(10)
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#define WDGCS_ULK BIT(11)
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#define WDOG_CS_PRES BIT(12)
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#define WDGCS_CMD32EN BIT(13)
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#define WDGCS_FLG BIT(14)
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#define WDGCS_INT BIT(6)
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#define WDG_BUS_CLK (0x0)
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#define WDG_LPO_CLK (0x1)
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#define WDG_32KHZ_CLK (0x2)
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#define WDG_EXT_CLK (0x3)
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#define CLK_RATE_1KHZ 1000
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#define CLK_RATE_32KHZ 125
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void hw_watchdog_set_timeout(u16 val)
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{
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/* setting timeout value */
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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writel(val, &wdog->toval);
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}
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void ulp_watchdog_reset(struct wdog_regs *wdog)
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{
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if (readl(&wdog->cs) & WDGCS_CMD32EN) {
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writel(REFRESH_WORD, &wdog->cnt);
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} else {
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dmb();
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__raw_writel(REFRESH_WORD0, &wdog->cnt);
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__raw_writel(REFRESH_WORD1, &wdog->cnt);
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dmb();
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}
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}
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void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)
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{
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u32 cmd32 = 0;
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if (readl(&wdog->cs) & WDGCS_CMD32EN) {
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writel(UNLOCK_WORD, &wdog->cnt);
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cmd32 = WDGCS_CMD32EN;
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} else {
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dmb();
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__raw_writel(UNLOCK_WORD0, &wdog->cnt);
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__raw_writel(UNLOCK_WORD1, &wdog->cnt);
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dmb();
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}
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/* Wait WDOG Unlock */
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while (!(readl(&wdog->cs) & WDGCS_ULK))
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;
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hw_watchdog_set_timeout(timeout);
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writel(0, &wdog->win);
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/* setting 1-kHz clock source, enable counter running, and clear interrupt */
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if (IS_ENABLED(CONFIG_ARCH_IMX9))
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writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) |
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WDGCS_FLG | WDOG_CS_PRES | WDGCS_INT), &wdog->cs);
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else
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writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) |
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WDGCS_FLG), &wdog->cs);
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/* Wait WDOG reconfiguration */
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while (!(readl(&wdog->cs) & WDGCS_RCS))
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;
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ulp_watchdog_reset(wdog);
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}
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void hw_watchdog_reset(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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ulp_watchdog_reset(wdog);
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}
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void hw_watchdog_init(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
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}
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void reset_cpu(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
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u32 cmd32 = 0;
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if (readl(&wdog->cs) & WDGCS_CMD32EN) {
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writel(UNLOCK_WORD, &wdog->cnt);
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cmd32 = WDGCS_CMD32EN;
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} else {
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dmb();
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__raw_writel(UNLOCK_WORD0, &wdog->cnt);
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__raw_writel(UNLOCK_WORD1, &wdog->cnt);
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dmb();
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}
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/* Wait WDOG Unlock */
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while (!(readl(&wdog->cs) & WDGCS_ULK))
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;
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hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout for imx93 */
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writel(0, &wdog->win);
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/* enable counter running */
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if (IS_ENABLED(CONFIG_ARCH_IMX9))
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writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES |
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WDGCS_INT), &wdog->cs);
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else
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writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
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/* Wait WDOG reconfiguration */
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while (!(readl(&wdog->cs) & WDGCS_RCS))
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;
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hw_watchdog_reset();
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while (1);
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}
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static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct ulp_wdt_priv *priv = dev_get_priv(dev);
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u64 timeout = 0;
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timeout = (timeout_ms * priv->clk_rate) / 1000;
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if (timeout > U16_MAX)
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return -EINVAL;
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ulp_watchdog_init(priv->wdog, (u16)timeout);
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return 0;
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}
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static int ulp_wdt_reset(struct udevice *dev)
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{
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struct ulp_wdt_priv *priv = dev_get_priv(dev);
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ulp_watchdog_reset(priv->wdog);
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return 0;
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}
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static int ulp_wdt_probe(struct udevice *dev)
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{
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struct ulp_wdt_priv *priv = dev_get_priv(dev);
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priv->wdog = dev_read_addr_ptr(dev);
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if (!priv->wdog)
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return -EINVAL;
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priv->clk_rate = (u32)dev_get_driver_data(dev);
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if (!priv->clk_rate)
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return -EINVAL;
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return 0;
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}
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static const struct wdt_ops ulp_wdt_ops = {
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.start = ulp_wdt_start,
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.reset = ulp_wdt_reset,
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};
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static const struct udevice_id ulp_wdt_ids[] = {
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{ .compatible = "fsl,imx7ulp-wdt", .data = CLK_RATE_1KHZ },
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{ .compatible = "fsl,imx8ulp-wdt", .data = CLK_RATE_1KHZ },
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{ .compatible = "fsl,imx93-wdt", .data = CLK_RATE_32KHZ },
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{}
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};
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U_BOOT_DRIVER(ulp_wdt) = {
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.name = "ulp_wdt",
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.id = UCLASS_WDT,
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.of_match = ulp_wdt_ids,
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.priv_auto = sizeof(struct ulp_wdt_priv),
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.probe = ulp_wdt_probe,
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.ops = &ulp_wdt_ops,
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};
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