mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
e1d1429b49
The SRD0_PFC0 register was not configured correctly to enable the GPIO's 49-63 for GPIO. They have been configured as trace signals. This patch fixes this by clearing the corresponding bit. Signed-off-by: Stefan Roese <sr@denx.de>
917 lines
25 KiB
C
917 lines
25 KiB
C
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <malloc.h>
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#include <command.h>
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#include <crc.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <status_led.h>
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#include <sha1.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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unsigned char sha1_checksum[SHA1_SUM_LEN];
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/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
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unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
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0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
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static void set_leds (int val)
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{
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out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
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}
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#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
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void __led_init (led_id_t mask, int state)
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{
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int val = GET_LEDS;
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if (state == STATUS_LED_ON)
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val |= mask;
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else
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val &= ~mask;
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set_leds (val);
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}
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void __led_set (led_id_t mask, int state)
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{
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int val = GET_LEDS;
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if (state == STATUS_LED_ON)
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val |= mask;
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else if (state == STATUS_LED_OFF)
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val &= ~mask;
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set_leds (val);
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}
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void __led_toggle (led_id_t mask)
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{
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int val = GET_LEDS;
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val ^= mask;
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set_leds (val);
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}
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static void status_led_blink (void)
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{
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int i;
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int val = GET_LEDS;
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/* set all LED which are on, to state BLINKING */
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for (i = 0; i < 4; i++) {
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if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING);
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else status_led_set (3 - i, STATUS_LED_OFF);
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val = val >> 1;
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}
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}
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#if defined(CONFIG_SHOW_BOOT_PROGRESS)
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void show_boot_progress (int val)
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{
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/* find all valid Codes for val in README */
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if (val == -30) return;
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if (val < 0) {
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/* smthing goes wrong */
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status_led_blink ();
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return;
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}
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switch (val) {
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case 1:
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/* validating Image */
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status_led_set (0, STATUS_LED_OFF);
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status_led_set (1, STATUS_LED_ON);
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status_led_set (2, STATUS_LED_ON);
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break;
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case 15:
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/* booting */
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status_led_set (0, STATUS_LED_ON);
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status_led_set (1, STATUS_LED_ON);
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status_led_set (2, STATUS_LED_ON);
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break;
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#if 0
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case 64:
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/* starting Ethernet configuration */
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status_led_set (0, STATUS_LED_OFF);
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status_led_set (1, STATUS_LED_OFF);
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status_led_set (2, STATUS_LED_ON);
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break;
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#endif
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case 80:
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/* loading Image */
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status_led_set (0, STATUS_LED_ON);
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status_led_set (1, STATUS_LED_OFF);
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status_led_set (2, STATUS_LED_ON);
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break;
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}
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}
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#endif
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int board_early_init_f(void)
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{
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register uint reg;
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set_leds(0); /* display boot info counter */
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(ebccfga, xbcfg);
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reg = mfdcr(ebccfgd);
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mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
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/*--------------------------------------------------------------------
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* GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c
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* via define from board config file.
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*-------------------------------------------------------------------*/
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000001); /* UIC1 crit is critical */
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mtdcr(uic0pr, 0xfffffe1f); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00000); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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* Setup other serial configuration
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*-------------------------------------------------------------------*/
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
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mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */
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mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
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return 0;
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}
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#define EEPROM_LEN 256
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void load_sernum_ethaddr (void)
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{
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int ret;
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char buf[EEPROM_LEN];
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char mac[32];
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char *use_eeprom;
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u16 checksumcrc16 = 0;
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/* read the MACs from EEprom */
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status_led_set (0, STATUS_LED_ON);
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status_led_set (1, STATUS_LED_ON);
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ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
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if (ret == 0) {
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checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2);
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/* check, if the EEprom is programmed:
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* - The Prefix(Byte 0,1,2) is equal to "ATR"
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* - The checksum, stored in the last 2 Bytes, is correct
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*/
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if ((strncmp (buf,"ATR",3) != 0) ||
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((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
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((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
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/* EEprom is not programmed */
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printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
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} else {
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/* get the MACs */
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sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
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buf[3],
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buf[4],
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buf[5],
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buf[6],
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buf[7],
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buf[8]);
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setenv ("ethaddr", (char *) mac);
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sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
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buf[9],
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buf[10],
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buf[11],
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buf[12],
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buf[13],
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buf[14]);
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setenv ("eth1addr", (char *) mac);
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return;
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}
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}
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/* some error reading the EEprom */
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if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
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/* dont use bootcmd */
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setenv("bootdelay", "-1");
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return;
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}
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/* == default ? use standard */
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if (strncmp (use_eeprom, "default", 7) == 0) {
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return;
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}
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/* Env doesnt exist -> hang */
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status_led_blink ();
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/* here we do this "handy" because we have no interrupts
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at this time */
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puts ("### EEPROM ERROR ### Please RESET the board ###\n");
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for (;;) {
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__led_toggle (12);
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udelay (100000);
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}
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return;
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}
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#ifdef CONFIG_PREBOOT
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static uchar kbd_magic_prefix[] = "key_magic";
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static uchar kbd_command_prefix[] = "key_cmd";
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struct kbd_data_t {
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char s1;
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char s2;
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};
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struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
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{
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char *val;
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unsigned long tmp;
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/* use the DIPs for some bootoptions */
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val = getenv (ENV_NAME_DIP);
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tmp = simple_strtoul (val, NULL, 16);
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kbd_data->s2 = (tmp & 0x0f);
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kbd_data->s1 = (tmp & 0xf0) >> 4;
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return kbd_data;
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}
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static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
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{
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char s1 = str[0];
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if (s1 >= '0' && s1 <= '9')
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s1 -= '0';
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else if (s1 >= 'a' && s1 <= 'f')
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s1 = s1 - 'a' + 10;
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else if (s1 >= 'A' && s1 <= 'F')
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s1 = s1 - 'A' + 10;
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else
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return -1;
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if (s1 != kbd_data->s1) return -1;
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s1 = str[1];
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if (s1 >= '0' && s1 <= '9')
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s1 -= '0';
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else if (s1 >= 'a' && s1 <= 'f')
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s1 = s1 - 'a' + 10;
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else if (s1 >= 'A' && s1 <= 'F')
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s1 = s1 - 'A' + 10;
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else
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return -1;
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if (s1 != kbd_data->s2) return -1;
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return 0;
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}
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static char *key_match (const struct kbd_data_t *kbd_data)
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{
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char magic[sizeof (kbd_magic_prefix) + 1];
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char *suffix;
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char *kbd_magic_keys;
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/*
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* The following string defines the characters that can be appended
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* to "key_magic" to form the names of environment variables that
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* hold "magic" key codes, i. e. such key codes that can cause
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* pre-boot actions. If the string is empty (""), then only
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* "key_magic" is checked (old behaviour); the string "125" causes
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* checks for "key_magic1", "key_magic2" and "key_magic5", etc.
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*/
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if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
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kbd_magic_keys = "";
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/* loop over all magic keys;
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* use '\0' suffix in case of empty string
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*/
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for (suffix = kbd_magic_keys; *suffix ||
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suffix == kbd_magic_keys; ++suffix) {
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sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
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if (compare_magic (kbd_data, getenv (magic)) == 0) {
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char cmd_name[sizeof (kbd_command_prefix) + 1];
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char *cmd;
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sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
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cmd = getenv (cmd_name);
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return (cmd);
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}
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}
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return (NULL);
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}
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#endif /* CONFIG_PREBOOT */
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static int pcs440ep_readinputs (void)
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{
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int i;
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char value[20];
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/* read the inputs and set the Envvars */
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/* Revision Level Bit 26 - 29 */
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i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
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i = swapbits[i];
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sprintf (value, "%02x", i);
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setenv (ENV_NAME_REVLEV, value);
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/* Solder Switch Bit 30 - 33 */
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i = (in32 (GPIO0_IR) & 0x00000003) << 2;
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i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
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i = swapbits[i];
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sprintf (value, "%02x", i);
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setenv (ENV_NAME_SOLDER, value);
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/* DIP Switch Bit 49 - 56 */
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i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
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i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
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sprintf (value, "%02x", i);
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setenv (ENV_NAME_DIP, value);
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return 0;
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}
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#if defined(CONFIG_SHA1_CHECK_UB_IMG)
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/*************************************************************************
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* calculate a SHA1 sum for the U-Boot image in Flash.
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*
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************************************************************************/
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static int pcs440ep_sha1 (int docheck)
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{
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unsigned char *data;
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unsigned char *ptroff;
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unsigned char output[20];
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unsigned char org[20];
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int i, len = CONFIG_SHA1_LEN;
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memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
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data = (unsigned char *)CFG_LOAD_ADDR;
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ptroff = &data[len + SHA1_SUM_POS];
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for (i = 0; i < SHA1_SUM_LEN; i++) {
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org[i] = ptroff[i];
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ptroff[i] = 0;
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}
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sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
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if (docheck == 2) {
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for (i = 0; i < 20 ; i++) {
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printf("%02X ", output[i]);
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}
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printf("\n");
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}
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if (docheck == 1) {
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for (i = 0; i < 20 ; i++) {
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if (org[i] != output[i]) return 1;
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}
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}
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return 0;
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}
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/*************************************************************************
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* do some checks after the SHA1 checksum from the U-Boot Image was
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* calculated.
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*
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************************************************************************/
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static void pcs440ep_checksha1 (void)
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{
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int ret;
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char *cs_test;
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status_led_set (0, STATUS_LED_OFF);
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status_led_set (1, STATUS_LED_OFF);
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status_led_set (2, STATUS_LED_ON);
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ret = pcs440ep_sha1 (1);
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if (ret == 0) return;
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if ((cs_test = getenv ("cs_test")) == NULL) {
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/* Env doesnt exist -> hang */
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status_led_blink ();
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/* here we do this "handy" because we have no interrupts
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at this time */
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puts ("### SHA1 ERROR ### Please RESET the board ###\n");
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for (;;) {
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__led_toggle (2);
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udelay (100000);
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}
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}
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if (strncmp (cs_test, "off", 3) == 0) {
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printf ("SHA1 U-Boot sum NOT ok!\n");
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setenv ("bootdelay", "-1");
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}
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}
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#else
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static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
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#endif
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int misc_init_r (void)
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{
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uint pbcr;
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int size_val = 0;
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/* Re-do sizing to get full correct info */
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mtdcr(ebccfga, pb0cr);
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pbcr = mfdcr(ebccfgd);
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switch (gd->bd->bi_flashsize) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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case 32 << 20:
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size_val = 5;
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break;
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case 64 << 20:
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size_val = 6;
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break;
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case 128 << 20:
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size_val = 7;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtdcr(ebccfga, pb0cr);
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mtdcr(ebccfgd, pbcr);
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[1]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
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&flash_info[1]);
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pcs440ep_readinputs ();
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pcs440ep_checksha1 ();
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#ifdef CONFIG_PREBOOT
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|
{
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struct kbd_data_t kbd_data;
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/* Decode keys */
|
|
char *str = strdup (key_match (get_keys (&kbd_data)));
|
|
/* Set or delete definition */
|
|
setenv ("preboot", str);
|
|
free (str);
|
|
}
|
|
#endif /* CONFIG_PREBOOT */
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
char *s = getenv("serial#");
|
|
|
|
printf("Board: PCS440EP");
|
|
if (s != NULL) {
|
|
puts(", serial# ");
|
|
puts(s);
|
|
}
|
|
putc('\n');
|
|
|
|
return (0);
|
|
}
|
|
|
|
void spd_ddr_init_hang (void)
|
|
{
|
|
status_led_set (0, STATUS_LED_OFF);
|
|
status_led_set (1, STATUS_LED_ON);
|
|
/* we cannot use hang() because we are still running from
|
|
Flash, and so the status_led driver is not initialized */
|
|
puts ("### SDRAM ERROR ### Please RESET the board ###\n");
|
|
for (;;) {
|
|
__led_toggle (4);
|
|
udelay (100000);
|
|
}
|
|
}
|
|
|
|
long int initdram (int board_type)
|
|
{
|
|
long dram_size = 0;
|
|
|
|
status_led_set (0, STATUS_LED_ON);
|
|
status_led_set (1, STATUS_LED_OFF);
|
|
dram_size = spd_sdram();
|
|
status_led_set (0, STATUS_LED_OFF);
|
|
status_led_set (1, STATUS_LED_ON);
|
|
if (dram_size == 0) {
|
|
hang();
|
|
}
|
|
|
|
return dram_size;
|
|
}
|
|
|
|
#if defined(CFG_DRAM_TEST)
|
|
int testdram(void)
|
|
{
|
|
unsigned long *mem = (unsigned long *)0;
|
|
const unsigned long kend = (1024 / sizeof(unsigned long));
|
|
unsigned long k, n;
|
|
|
|
mtmsr(0);
|
|
|
|
for (k = 0; k < CFG_KBYTES_SDRAM;
|
|
++k, mem += (1024 / sizeof(unsigned long))) {
|
|
if ((k & 1023) == 0) {
|
|
printf("%3d MB\r", k / 1024);
|
|
}
|
|
|
|
memset(mem, 0xaaaaaaaa, 1024);
|
|
for (n = 0; n < kend; ++n) {
|
|
if (mem[n] != 0xaaaaaaaa) {
|
|
printf("SDRAM test fails at: %08x\n",
|
|
(uint) & mem[n]);
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
memset(mem, 0x55555555, 1024);
|
|
for (n = 0; n < kend; ++n) {
|
|
if (mem[n] != 0x55555555) {
|
|
printf("SDRAM test fails at: %08x\n",
|
|
(uint) & mem[n]);
|
|
return 1;
|
|
}
|
|
}
|
|
}
|
|
printf("SDRAM test passes\n");
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*************************************************************************
|
|
* pci_pre_init
|
|
*
|
|
* This routine is called just prior to registering the hose and gives
|
|
* the board the opportunity to check things. Returning a value of zero
|
|
* indicates that things are bad & PCI initialization should be aborted.
|
|
*
|
|
* Different boards may wish to customize the pci controller structure
|
|
* (add regions, override default access routines, etc) or perform
|
|
* certain pre-initialization actions.
|
|
*
|
|
************************************************************************/
|
|
#if defined(CONFIG_PCI)
|
|
int pci_pre_init(struct pci_controller *hose)
|
|
{
|
|
unsigned long addr;
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| Set priority for all PLB3 devices to 0.
|
|
| Set PLB3 arbiter to fair mode.
|
|
+-------------------------------------------------------------------------*/
|
|
mfsdr(sdr_amp1, addr);
|
|
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
|
addr = mfdcr(plb3_acr);
|
|
mtdcr(plb3_acr, addr | 0x80000000);
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| Set priority for all PLB4 devices to 0.
|
|
+-------------------------------------------------------------------------*/
|
|
mfsdr(sdr_amp0, addr);
|
|
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
|
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
|
mtdcr(plb4_acr, addr);
|
|
|
|
/*-------------------------------------------------------------------------+
|
|
| Set Nebula PLB4 arbiter to fair mode.
|
|
+-------------------------------------------------------------------------*/
|
|
/* Segment0 */
|
|
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
|
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
|
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
|
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
|
|
mtdcr(plb0_acr, addr);
|
|
|
|
/* Segment1 */
|
|
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
|
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
|
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
|
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
|
mtdcr(plb1_acr, addr);
|
|
|
|
return 1;
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
/*************************************************************************
|
|
* pci_target_init
|
|
*
|
|
* The bootstrap configuration provides default settings for the pci
|
|
* inbound map (PIM). But the bootstrap config choices are limited and
|
|
* may not be sufficient for a given board.
|
|
*
|
|
************************************************************************/
|
|
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
|
void pci_target_init(struct pci_controller *hose)
|
|
{
|
|
/*--------------------------------------------------------------------------+
|
|
* Set up Direct MMIO registers
|
|
*--------------------------------------------------------------------------*/
|
|
/*--------------------------------------------------------------------------+
|
|
| PowerPC440 EP PCI Master configuration.
|
|
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
|
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
|
|
| Use byte reversed out routines to handle endianess.
|
|
| Make this region non-prefetchable.
|
|
+--------------------------------------------------------------------------*/
|
|
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
|
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
|
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
|
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
|
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
|
|
|
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
|
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
|
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
|
|
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
|
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
|
|
|
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
|
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
|
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
|
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
|
|
|
/*--------------------------------------------------------------------------+
|
|
* Set up Configuration registers
|
|
*--------------------------------------------------------------------------*/
|
|
|
|
/* Program the board's subsystem id/vendor id */
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
|
CFG_PCI_SUBSYS_VENDORID);
|
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
|
|
|
/* Configure command register as bus master */
|
|
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
|
|
|
/* 240nS PCI clock */
|
|
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
|
|
|
/* No error reporting */
|
|
pci_write_config_word(0, PCI_ERREN, 0);
|
|
|
|
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
|
|
|
}
|
|
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
|
|
|
/*************************************************************************
|
|
* pci_master_init
|
|
*
|
|
************************************************************************/
|
|
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
|
void pci_master_init(struct pci_controller *hose)
|
|
{
|
|
unsigned short temp_short;
|
|
|
|
/*--------------------------------------------------------------------------+
|
|
| Write the PowerPC440 EP PCI Configuration regs.
|
|
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
|
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
|
+--------------------------------------------------------------------------*/
|
|
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
|
pci_write_config_word(0, PCI_COMMAND,
|
|
temp_short | PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY);
|
|
}
|
|
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
|
|
|
/*************************************************************************
|
|
* is_pci_host
|
|
*
|
|
* This routine is called to determine if a pci scan should be
|
|
* performed. With various hardware environments (especially cPCI and
|
|
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
|
* bit in the strap register, or generic host/adapter assumptions.
|
|
*
|
|
* Rather than hard-code a bad assumption in the general 440 code, the
|
|
* 440 pci code requires the board to decide at runtime.
|
|
*
|
|
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
|
*
|
|
*
|
|
************************************************************************/
|
|
#if defined(CONFIG_PCI)
|
|
int is_pci_host(struct pci_controller *hose)
|
|
{
|
|
/* PCS440EP is always configured as host. */
|
|
return (1);
|
|
}
|
|
#endif /* defined(CONFIG_PCI) */
|
|
|
|
/*************************************************************************
|
|
* hw_watchdog_reset
|
|
*
|
|
* This routine is called to reset (keep alive) the watchdog timer
|
|
*
|
|
************************************************************************/
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
void hw_watchdog_reset(void)
|
|
{
|
|
|
|
}
|
|
#endif
|
|
|
|
/*************************************************************************
|
|
* "led" Commando for the U-Boot shell
|
|
*
|
|
************************************************************************/
|
|
int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
int rcode = 0, i;
|
|
ulong pattern = 0;
|
|
|
|
pattern = simple_strtoul (argv[1], NULL, 16);
|
|
if (pattern > 0x400) {
|
|
int val = GET_LEDS;
|
|
printf ("led: %x\n", val);
|
|
return rcode;
|
|
}
|
|
if (pattern > 0x200) {
|
|
status_led_blink ();
|
|
hang ();
|
|
return rcode;
|
|
}
|
|
if (pattern > 0x100) {
|
|
status_led_blink ();
|
|
return rcode;
|
|
}
|
|
pattern &= 0x0f;
|
|
for (i = 0; i < 4; i++) {
|
|
if (pattern & 0x01) status_led_set (i, STATUS_LED_ON);
|
|
else status_led_set (i, STATUS_LED_OFF);
|
|
pattern = pattern >> 1;
|
|
}
|
|
return rcode;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
led, 2, 1, do_led,
|
|
"led [bitmask] - set the DIAG-LED\n",
|
|
"[bitmask] 0x01 = DIAG 1 on\n"
|
|
" 0x02 = DIAG 2 on\n"
|
|
" 0x04 = DIAG 3 on\n"
|
|
" 0x08 = DIAG 4 on\n"
|
|
" > 0x100 set the LED, who are on, to state blinking\n"
|
|
);
|
|
|
|
#if defined(CONFIG_SHA1_CHECK_UB_IMG)
|
|
/*************************************************************************
|
|
* "sha1" Commando for the U-Boot shell
|
|
*
|
|
************************************************************************/
|
|
int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|
{
|
|
int rcode = -1;
|
|
|
|
if (argc < 2) {
|
|
usage:
|
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
|
return 1;
|
|
}
|
|
|
|
if (argc >= 3) {
|
|
unsigned char *data;
|
|
unsigned char output[20];
|
|
int len;
|
|
int i;
|
|
|
|
data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
|
|
len = simple_strtoul (argv[2], NULL, 16);
|
|
sha1_csum (data, len, (unsigned char *)output);
|
|
printf ("U-Boot sum:\n");
|
|
for (i = 0; i < 20 ; i++) {
|
|
printf ("%02X ", output[i]);
|
|
}
|
|
printf ("\n");
|
|
if (argc == 4) {
|
|
data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
|
|
memcpy (data, output, 20);
|
|
}
|
|
return 0;
|
|
}
|
|
if (argc == 2) {
|
|
char *ptr = argv[1];
|
|
if (*ptr != '-') goto usage;
|
|
ptr++;
|
|
if ((*ptr == 'c') || (*ptr == 'C')) {
|
|
rcode = pcs440ep_sha1 (1);
|
|
printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
|
|
} else if ((*ptr == 'p') || (*ptr == 'P')) {
|
|
rcode = pcs440ep_sha1 (2);
|
|
} else {
|
|
rcode = pcs440ep_sha1 (0);
|
|
}
|
|
return rcode;
|
|
}
|
|
return rcode;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
sha1, 4, 1, do_sha1,
|
|
"sha1 - calculate the SHA1 Sum\n",
|
|
"address len [addr] calculate the SHA1 sum [save at addr]\n"
|
|
" -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
|
|
" -c check the U-Boot image in flash\n"
|
|
);
|
|
#endif
|
|
|
|
#if defined (CONFIG_CMD_IDE)
|
|
/* These addresses need to be shifted one place to the left
|
|
* ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
|
|
* These values are shifted
|
|
*/
|
|
extern ulong *ide_bus_offset;
|
|
void inline ide_outb(int dev, int port, unsigned char val)
|
|
{
|
|
debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
|
|
dev, port, val, (ATA_CURR_BASE(dev)+port));
|
|
|
|
out_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)), val);
|
|
}
|
|
unsigned char inline ide_inb(int dev, int port)
|
|
{
|
|
uchar val;
|
|
val = in_be16((u16 *)(ATA_CURR_BASE(dev)+(port << 1)));
|
|
debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
|
|
dev, port, (ATA_CURR_BASE(dev)+port), val);
|
|
return (val);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_IDE_PREINIT
|
|
int ide_preinit (void)
|
|
{
|
|
/* Set True IDE Mode */
|
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
|
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
|
|
out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
|
|
udelay (100000);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
|
|
void ide_set_reset (int idereset)
|
|
{
|
|
debug ("ide_reset(%d)\n", idereset);
|
|
if (idereset == 0) {
|
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
|
|
} else {
|
|
out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
|
|
}
|
|
udelay (10000);
|
|
}
|
|
#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
|