mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 22:20:45 +00:00
4dcdc5c159
This patch fix mmc driver abort caused by below patch:
3d296365e4 mmc: sdhci: Add support for sdhci-caps-mask
After the patch sdhci_setup_cfg() access to host->mmc->dev,
so we have to do init before make the call to the function()
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
|
|
*
|
|
* Rockchip SD Host Controller Interface
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <dt-structs.h>
|
|
#include <linux/libfdt.h>
|
|
#include <malloc.h>
|
|
#include <mapmem.h>
|
|
#include <sdhci.h>
|
|
#include <clk.h>
|
|
|
|
/* 400KHz is max freq for card ID etc. Use that as min */
|
|
#define EMMC_MIN_FREQ 400000
|
|
|
|
struct rockchip_sdhc_plat {
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
|
|
#endif
|
|
struct mmc_config cfg;
|
|
struct mmc mmc;
|
|
};
|
|
|
|
struct rockchip_sdhc {
|
|
struct sdhci_host host;
|
|
void *base;
|
|
};
|
|
|
|
static int arasan_sdhci_probe(struct udevice *dev)
|
|
{
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
|
|
struct rockchip_sdhc *prv = dev_get_priv(dev);
|
|
struct sdhci_host *host = &prv->host;
|
|
int max_frequency, ret;
|
|
struct clk clk;
|
|
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
|
|
|
|
host->name = dev->name;
|
|
host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
|
|
max_frequency = dtplat->max_frequency;
|
|
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
|
|
#else
|
|
max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
|
|
ret = clk_get_by_index(dev, 0, &clk);
|
|
#endif
|
|
if (!ret) {
|
|
ret = clk_set_rate(&clk, max_frequency);
|
|
if (IS_ERR_VALUE(ret))
|
|
printf("%s clk set rate fail!\n", __func__);
|
|
} else {
|
|
printf("%s fail to get clk\n", __func__);
|
|
}
|
|
|
|
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
|
|
host->max_clk = max_frequency;
|
|
/*
|
|
* The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
|
|
* doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
|
|
* check for other bus-width values.
|
|
*/
|
|
if (host->bus_width == 8)
|
|
host->host_caps |= MMC_MODE_8BIT;
|
|
|
|
host->mmc = &plat->mmc;
|
|
host->mmc->priv = &prv->host;
|
|
host->mmc->dev = dev;
|
|
upriv->mmc = host->mmc;
|
|
|
|
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return sdhci_probe(dev);
|
|
}
|
|
|
|
static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
struct sdhci_host *host = dev_get_priv(dev);
|
|
|
|
host->name = dev->name;
|
|
host->ioaddr = dev_read_addr_ptr(dev);
|
|
host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_sdhci_bind(struct udevice *dev)
|
|
{
|
|
struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
|
|
|
|
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
static const struct udevice_id arasan_sdhci_ids[] = {
|
|
{ .compatible = "arasan,sdhci-5.1" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(arasan_sdhci_drv) = {
|
|
.name = "rockchip_rk3399_sdhci_5_1",
|
|
.id = UCLASS_MMC,
|
|
.of_match = arasan_sdhci_ids,
|
|
.ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
|
|
.ops = &sdhci_ops,
|
|
.bind = rockchip_sdhci_bind,
|
|
.probe = arasan_sdhci_probe,
|
|
.priv_auto_alloc_size = sizeof(struct rockchip_sdhc),
|
|
.platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat),
|
|
};
|