mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
ef531c7357
- update readme. - add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315 ucode from NOR/NAND/SPI/SD/REMOTE. - update cpld vbank with SW3[5:7]=000 as default vbank0 instead of previous SW3[5:7]=111 as default vbank. - fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
42 lines
1.5 KiB
C
42 lines
1.5 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPLD register set of T2080RDB board-specific.
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*/
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struct cpld_data {
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u8 chip_id1; /* 0x00 - Chip ID1 register */
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u8 chip_id2; /* 0x01 - Chip ID2 register */
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u8 hw_ver; /* 0x02 - Hardware Revision Register */
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u8 sw_ver; /* 0x03 - Software Revision register */
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u8 res0[12]; /* 0x04 - 0x0F - not used */
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u8 reset_ctl; /* 0x10 - Reset control Register */
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u8 flash_csr; /* 0x11 - Flash control and status register */
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u8 thermal_csr; /* 0x12 - Thermal control and status register */
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u8 led_csr; /* 0x13 - LED control and status register */
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u8 sfp_csr; /* 0x14 - SFP+ control and status register */
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u8 misc_csr; /* 0x15 - Misc control and status register */
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u8 boot_or; /* 0x16 - Boot config override register */
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u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
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u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
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} cpld_data_t;
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) \
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cpld_write(offsetof(struct cpld_data, reg), value)
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/* CPLD on IFC */
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#define CPLD_LBMAP_MASK 0x3F
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_OVERRIDE 0x40
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#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
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#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
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#define CPLD_LBMAP_RESET 0xFF
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#define CPLD_LBMAP_SHIFT 0x03
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#define CPLD_BOOT_SEL 0x80
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