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5614e71b49
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
34 lines
965 B
C
34 lines
965 B
C
/*
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* Copyright 2009-2010 eXMeritus, A Boeing Company
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* Copyright 2008-2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* We only support one DIMM, so according to the P2020 docs we should
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* set the options as follows:
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*/
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popts->cs_local_opts[0].odt_rd_cfg = 0;
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popts->cs_local_opts[0].odt_wr_cfg = 4;
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popts->cs_local_opts[1].odt_rd_cfg = 0;
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popts->cs_local_opts[1].odt_wr_cfg = 0;
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popts->half_strength_driver_enable = 0;
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/* Manually configured for our static clock rate */
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popts->clk_adjust = 4;
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popts->cpo_override = 4;
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popts->write_data_delay = 2;
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popts->twot_en = 0;
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}
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