mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-12 14:23:00 +00:00
1146dc0854
k3-am62* SoC dtsi files now provide the following: bootph-all: dmss secure_proxy_main dmsc k3_pds k3_clks k3_reset main_pmx0 main_timer0 mcu_pmx0 wkup_conf chipid bootph-pre-ram: secure_proxy_sa3 main_esm mcu_esm Drop these from board r5 and u-boot.dtsi files as these are duplicate in them now. Acked-by: Francesco Dolcini <francesco.dolcini@toradex.com> Tested-by: Dhruva Gole <d-gole@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
140 lines
2 KiB
Text
140 lines
2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Common AM625 SK dts file for SPLs
|
|
* Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
#include "k3-am625-sk-binman.dtsi"
|
|
|
|
/ {
|
|
chosen {
|
|
stdout-path = "serial2:115200n8";
|
|
tick-timer = &main_timer0;
|
|
};
|
|
|
|
aliases {
|
|
mmc1 = &sdhci1;
|
|
};
|
|
|
|
memory@80000000 {
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
&main_conf {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_timer0 {
|
|
clock-frequency = <25000000>;
|
|
};
|
|
|
|
&main_uart0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_uart0_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&sdhci1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_mmc1_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&fss {
|
|
bootph-all;
|
|
};
|
|
|
|
&ospi0_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&ospi0 {
|
|
bootph-all;
|
|
|
|
flash@0 {
|
|
bootph-all;
|
|
|
|
partitions {
|
|
bootph-all;
|
|
|
|
partition@3fc0000 {
|
|
bootph-all;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&inta_main_dmss {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_bcdma {
|
|
reg = <0x00 0x485c0100 0x00 0x100>,
|
|
<0x00 0x4c000000 0x00 0x20000>,
|
|
<0x00 0x4a820000 0x00 0x20000>,
|
|
<0x00 0x4aa40000 0x00 0x20000>,
|
|
<0x00 0x4bc00000 0x00 0x100000>,
|
|
<0x00 0x48600000 0x00 0x8000>,
|
|
<0x00 0x484a4000 0x00 0x2000>,
|
|
<0x00 0x484c2000 0x00 0x2000>;
|
|
reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt",
|
|
"ringrt" , "cfg", "tchan", "rchan";
|
|
};
|
|
|
|
&main_pktdma {
|
|
reg = <0x00 0x485c0000 0x00 0x100>,
|
|
<0x00 0x4a800000 0x00 0x20000>,
|
|
<0x00 0x4aa00000 0x00 0x20000>,
|
|
<0x00 0x4b800000 0x00 0x200000>,
|
|
<0x00 0x485e0000 0x00 0x10000>,
|
|
<0x00 0x484a0000 0x00 0x2000>,
|
|
<0x00 0x484c0000 0x00 0x2000>,
|
|
<0x00 0x48430000 0x00 0x1000>;
|
|
reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
|
|
"cfg", "tchan", "rchan", "rflow";
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw3g_mdio {
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw3g_phy0 {
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw3g_phy1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_rgmii1_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&main_rgmii2_pins_default {
|
|
bootph-all;
|
|
};
|
|
|
|
&phy_gmii_sel {
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw3g {
|
|
bootph-all;
|
|
ethernet-ports {
|
|
bootph-all;
|
|
};
|
|
};
|
|
|
|
&cpsw_port1 {
|
|
bootph-all;
|
|
};
|
|
|
|
&cpsw_port2 {
|
|
status = "disabled";
|
|
};
|