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1115cd2de7
Implement macro SOCFPGA_RESET(name), which produces an abstract reset number. Implement macros which allow extracting the reset offset in permodrstN register and which permodrstN register the reset is located in from this abstract reset number. Use these macros throughout the reset manager. Signed-off-by: Marek Vasut <marex@denx.de>
139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/fpga_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
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void socfpga_watchdog_reset(void)
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{
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/* assert reset for watchdog */
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setbits_le32(&reset_manager_base->per_mod_reset,
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1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
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/* deassert watchdog from reset (watchdog in not running state) */
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clrbits_le32(&reset_manager_base->per_mod_reset,
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1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
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}
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/*
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* Write the reset manager register to cause reset
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*/
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void reset_cpu(ulong addr)
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{
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/* request a warm reset */
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writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
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&reset_manager_base->ctrl);
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/*
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* infinite loop here as watchdog will trigger and reset
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* the processor
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*/
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while (1)
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;
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}
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/*
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* Release peripherals from reset based on handoff
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*/
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void reset_deassert_peripherals_handoff(void)
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{
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writel(0, &reset_manager_base->per_mod_reset);
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}
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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void socfpga_bridges_reset(int enable)
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{
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/* For SoCFPGA-VT, this is NOP. */
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}
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#else
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#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
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#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
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#define L3REGS_REMAP_OCRAM_MASK 0x01
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void socfpga_bridges_reset(int enable)
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{
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const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
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L3REGS_REMAP_HPS2FPGA_MASK |
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L3REGS_REMAP_OCRAM_MASK;
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if (enable) {
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/* brdmodrst */
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writel(0xffffffff, &reset_manager_base->brg_mod_reset);
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} else {
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/* Check signal from FPGA. */
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if (fpgamgr_poll_fpga_ready()) {
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/* FPGA not ready. Wait for watchdog timeout. */
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printf("%s: fpga not ready, hanging.\n", __func__);
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hang();
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}
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/* brdmodrst */
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writel(0, &reset_manager_base->brg_mod_reset);
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/* Remap the bridges into memory map */
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writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
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}
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}
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#endif
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/* Change the reset state for EMAC 0 and EMAC 1 */
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void socfpga_emac_reset(int enable)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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if (enable) {
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setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
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setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
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} else {
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#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
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clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
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#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
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clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
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#endif
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}
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}
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/* SPI Master enable (its held in reset by the preloader) */
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void socfpga_spim_enable(void)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) |
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(1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1))));
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}
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/* Bring UART0 out of reset. */
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void socfpga_uart0_enable(void)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0)));
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}
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/* Bring SDRAM controller out of reset. */
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void socfpga_sdram_enable(void)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR)));
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}
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/* Bring OSC1 timer out of reset. */
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void socfpga_osc1timer_enable(void)
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{
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const void *reset = &reset_manager_base->per_mod_reset;
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clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0)));
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}
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