mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 05:42:58 +00:00
10ff7e6b04
Synchronise the USB device tree definition with Linux, allowing the U-Boot control FDT to be used to boot a Linux system with working USB. An extra compatible string, "fsl,layerscape-dwc3" is needed for special handling in U-Boot, so has been added to the -u-boot.dtsi file. It might be better to add this to the Linux source bindings. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
664 lines
18 KiB
Text
664 lines
18 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1088a SOC common device tree source
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*
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* Copyright 2017, 2020-2021, 2023 NXP
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*/
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#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "fsl,ls1088a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* We have 2 clusters having 4 Cortex-A53 cores each */
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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CPU_PH20: cpu-ph20 {
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compatible = "arm,idle-state";
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idle-state-name = "PH20";
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arm,psci-suspend-param = <0x0>;
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entry-latency-us = <1000>;
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exit-latency-us = <1000>;
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min-residency-us = <3000>;
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};
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
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<0x0 0x0c0c0000 0 0x2000>, /* GICC */
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<0x0 0x0c0d0000 0 0x1000>, /* GICH */
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<0x0 0x0c0e0000 0 0x20000>; /* GICV */
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interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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its: gic-its@6020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x6020000 0 0x20000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
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clockgen: clocking@1300000 {
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compatible = "fsl,ls1088a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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duart0: serial@21c0500 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(4)>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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duart1: serial@21c0600 {
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(4)>;
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interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gpio0: gpio@2300000 {
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compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2300000 0x0 0x10000>;
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interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2310000 {
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compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2310000 0x0 0x10000>;
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interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@2320000 {
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compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2320000 0x0 0x10000>;
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@2330000 {
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compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
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reg = <0x0 0x2330000 0x0 0x10000>;
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interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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i2c0: i2c@2000000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(8)>;
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status = "disabled";
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};
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i2c1: i2c@2010000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2010000 0x0 0x10000>;
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interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(8)>;
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status = "disabled";
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};
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i2c2: i2c@2020000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2020000 0x0 0x10000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(8)>;
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status = "disabled";
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};
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i2c3: i2c@2030000 {
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compatible = "fsl,vf610-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2030000 0x0 0x10000>;
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interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
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QORIQ_CLK_PLL_DIV(8)>;
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status = "disabled";
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};
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usb0: usb@3100000 {
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compatible = "snps,dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
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status = "disabled";
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};
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usb1: usb@3110000 {
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compatible = "snps,dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
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status = "disabled";
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};
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pcie1: pcie@3400000 {
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compatible = "fsl,ls1088a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
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<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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interrupt-names = "aer";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-viewport = <256>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
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iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
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status = "disabled";
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};
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pcie_ep1: pcie-ep@3400000 {
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compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
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reg = <0x00 0x03400000 0x0 0x00100000>,
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<0x20 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ib-windows = <24>;
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num-ob-windows = <256>;
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max-functions = /bits/ 8 <2>;
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status = "disabled";
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};
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pcie2: pcie@3500000 {
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compatible = "fsl,ls1088a-pcie";
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reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
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<0x28 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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interrupt-names = "aer";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-viewport = <6>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
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iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
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status = "disabled";
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};
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pcie_ep2: pcie-ep@3500000 {
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compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
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reg = <0x00 0x03500000 0x0 0x00100000>,
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<0x28 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ib-windows = <6>;
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num-ob-windows = <6>;
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status = "disabled";
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};
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pcie3: pcie@3600000 {
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compatible = "fsl,ls1088a-pcie";
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reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
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<0x30 0x00000000 0x0 0x00002000>; /* configuration space */
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reg-names = "regs", "config";
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interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
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interrupt-names = "aer";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-viewport = <6>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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msi-parent = <&its>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
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<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
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iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
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status = "disabled";
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};
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pcie_ep3: pcie-ep@3600000 {
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compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
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reg = <0x00 0x03600000 0x0 0x00100000>,
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<0x30 0x00000000 0x8 0x00000000>;
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reg-names = "regs", "addr_space";
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num-ib-windows = <6>;
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num-ob-windows = <6>;
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status = "disabled";
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};
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smmu: iommu@5000000 {
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compatible = "arm,mmu-500";
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reg = <0 0x5000000 0 0x800000>;
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#iommu-cells = <1>;
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stream-match-mask = <0x7C00>;
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dma-coherent;
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#global-interrupts = <12>;
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// global secure fault
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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// combined secure
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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// global non-secure fault
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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// combined non-secure
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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// performance counter interrupts 0-7
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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// per context interrupt, 64 interrupts
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
dspi: dspi@2100000 {
|
|
compatible = "fsl,vf610-dspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2100000 0x0 0x10000>;
|
|
interrupts = <0 26 0x4>; /* Level high type */
|
|
spi-num-chipselects = <6>;
|
|
};
|
|
|
|
qspi: quadspi@1550000 {
|
|
compatible = "fsl,ls1088a-qspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
<0x0 0x20000000 0x0 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
status = "disabled";
|
|
};
|
|
|
|
esdhc: esdhc@2140000 {
|
|
compatible = "fsl,esdhc";
|
|
reg = <0x0 0x2140000 0x0 0x10000>;
|
|
interrupts = <0 28 0x4>; /* Level high type */
|
|
little-endian;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
ifc: ifc@1530000 {
|
|
compatible = "fsl,ifc", "simple-bus";
|
|
reg = <0x0 0x2240000 0x0 0x20000>;
|
|
interrupts = <0 21 0x4>; /* Level high type */
|
|
};
|
|
|
|
crypto: crypto@8000000 {
|
|
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
|
fsl,sec-era = <8>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x00 0x8000000 0x100000>;
|
|
reg = <0x00 0x8000000 0x0 0x100000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-coherent;
|
|
|
|
sec_jr0: jr@10000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x10000 0x10000>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr@20000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x20000 0x10000>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr2: jr@30000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr3: jr@40000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x40000 0x10000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
sata: sata@3200000 {
|
|
compatible = "fsl,ls1088a-ahci";
|
|
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
|
|
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
|
|
reg-names = "ahci", "sata-ecc";
|
|
interrupts = <0 133 4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
fsl_mc: fsl-mc@80c000000 {
|
|
compatible = "fsl,qoriq-mc", "simple-mfd";
|
|
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
|
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
|
#address-cells = <3>;
|
|
#size-cells = <1>;
|
|
|
|
/*
|
|
* Region type 0x0 - MC portals
|
|
* Region type 0x1 - QBMAN portals
|
|
*/
|
|
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
|
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
|
|
|
dpmacs {
|
|
compatible = "simple-mfd";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
dpmac1: dpmac@1 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac2: dpmac@2 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac3: dpmac@3 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac4: dpmac@4 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac5: dpmac@5 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac6: dpmac@6 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac7: dpmac@7 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac8: dpmac@8 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac9: dpmac@9 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dpmac10: dpmac@a {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xa>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
emdio1: mdio@8B96000 {
|
|
compatible = "fsl,ls-mdio";
|
|
reg = <0x0 0x8B96000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emdio2: mdio@8B97000 {
|
|
compatible = "fsl,ls-mdio";
|
|
reg = <0x0 0x8B97000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|