mirror of
https://github.com/AsahiLinux/u-boot
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194 lines
7.9 KiB
C
194 lines
7.9 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2009
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _U8500_I2C_H_
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#define _U8500_I2C_H_
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#include <asm/types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/u8500.h>
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struct u8500_i2c_regs {
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u32 cr; /* Control Register 0x00 */
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u32 scr; /* Slave Address Register 0x04 */
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u32 hsmcr; /* HS Master code Register 0x08 */
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u32 mcr; /* Master Control Register 0x0C */
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u32 tfr; /* Transmit Fifo Register 0x10 */
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u32 sr; /* Status Register 0x14 */
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u32 rfr; /* Receiver Fifo Register 0x18 */
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u32 tftr; /* Transmit Fifo Threshold Register 0x1C */
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u32 rftr; /* Receiver Fifo Threshold Register 0x20 */
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u32 dmar; /* DMA register 0x24 */
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u32 brcr; /* Baud Rate Counter Register 0x28 */
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u32 imscr; /* Interrupt Mask Set and Clear Register 0x2C */
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u32 risr; /* Raw interrupt status register 0x30 */
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u32 misr; /* Masked interrupt status register 0x34 */
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u32 icr; /* Interrupt Set and Clear Register 0x38 */
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u32 reserved_1[(0xFE0 - 0x3c) >> 2]; /* Reserved 0x03C to 0xFE0 */
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u32 periph_id_0; /* peripheral ID 0 0xFE0 */
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u32 periph_id_1; /* peripheral ID 1 0xFE4 */
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u32 periph_id_2; /* peripheral ID 2 0xFE8 */
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u32 periph_id_3; /* peripheral ID 3 0xFEC */
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u32 cell_id_0; /* I2C cell ID 0 0xFF0 */
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u32 cell_id_1; /* I2C cell ID 1 0xFF4 */
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u32 cell_id_2; /* I2C cell ID 2 0xFF8 */
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u32 cell_id_3; /* I2C cell ID 3 0xFFC */
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};
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/* Control Register */
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/* Mask values for control register mask */
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#define U8500_I2C_CR_PE 0x0001 /* Peripheral enable */
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#define U8500_I2C_CR_OM 0x0006 /* Operation mode */
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#define U8500_I2C_CR_SAM 0x0008 /* Slave Addressing mode */
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#define U8500_I2C_CR_SM 0x0030 /* Speed mode */
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#define U8500_I2C_CR_SGCM 0x0040 /* Slave General call mode */
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#define U8500_I2C_CR_FTX 0x0080 /* Flush Transmit */
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#define U8500_I2C_CR_FRX 0x0100 /* Flush Receive */
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#define U8500_I2C_CR_DMA_TX_EN 0x0200 /* DMA TX Enable */
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#define U8500_I2C_CR_DMA_RX_EN 0x0400 /* DMA Rx Enable */
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#define U8500_I2C_CR_DMA_SLE 0x0800 /* DMA Synchronization Logic enable */
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#define U8500_I2C_CR_LM 0x1000 /* Loop back mode */
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#define U8500_I2C_CR_FON 0x6000 /* Filtering On */
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/* shift valus for control register bit fields */
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#define U8500_I2C_CR_SHIFT_PE 0 /* Peripheral enable */
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#define U8500_I2C_CR_SHIFT_OM 1 /* Operation mode */
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#define U8500_I2C_CR_SHIFT_SAM 3 /* Slave Addressing mode */
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#define U8500_I2C_CR_SHIFT_SM 4 /* Speed mode */
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#define U8500_I2C_CR_SHIFT_SGCM 6 /* Slave General call mode */
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#define U8500_I2C_CR_SHIFT_FTX 7 /* Flush Transmit */
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#define U8500_I2C_CR_SHIFT_FRX 8 /* Flush Receive */
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#define U8500_I2C_CR_SHIFT_DMA_TX_EN 9 /* DMA TX Enable */
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#define U8500_I2C_CR_SHIFT_DMA_RX_EN 10 /* DMA Rx Enable */
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#define U8500_I2C_CR_SHIFT_DMA_SLE 11 /* DMA Synch Logic enable */
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#define U8500_I2C_CR_SHIFT_LM 12 /* Loop back mode */
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#define U8500_I2C_CR_SHIFT_FON 13 /* Filtering On */
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/* bus operation modes */
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#define U8500_I2C_BUS_SLAVE_MODE 0
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#define U8500_I2C_BUS_MASTER_MODE 1
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#define U8500_I2C_BUS_MASTER_SLAVE_MODE 2
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/* Slave control register*/
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/* Mask values slave control register */
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#define U8500_I2C_SCR_ADDR 0x3FF
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#define U8500_I2C_SCR_DATA_SETUP_TIME 0xFFFF0000
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/* Shift values for Slave control register */
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#define U8500_I2C_SCR_SHIFT_ADDR 0
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#define U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME 16
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/* Master Control Register */
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/* Mask values for Master control register */
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#define U8500_I2C_MCR_OP 0x00000001 /* Operation */
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#define U8500_I2C_MCR_A7 0x000000FE /* LSB bits of Address */
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#define U8500_I2C_MCR_EA10 0x00000700 /* Extended Address */
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#define U8500_I2C_MCR_SB 0x00000800 /* Start byte procedure */
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#define U8500_I2C_MCR_AM 0x00003000 /* Address type */
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#define U8500_I2C_MCR_STOP 0x00004000 /* stop condition */
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#define U8500_I2C_MCR_LENGTH 0x03FF8000 /* Frame length */
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#define U8500_I2C_MCR_A10 0x000007FE /* Enable 10 bit address */
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/* mask for length field,stop and operation */
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#define U8500_I2C_MCR_LENGTH_STOP_OP 0x3FFC001
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/* Shift values for Master control values */
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#define U8500_I2C_MCR_SHIFT_OP 0 /* Operation */
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#define U8500_I2C_MCR_SHIFT_A7 1 /* LSB bits of Address */
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#define U8500_I2C_MCR_SHIFT_EA10 8 /* Extended Address */
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#define U8500_I2C_MCR_SHIFT_SB 11 /* Start byte procedure */
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#define U8500_I2C_MCR_SHIFT_AM 12 /* Address type */
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#define U8500_I2C_MCR_SHIFT_STOP 14 /* stop condition */
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#define U8500_I2C_MCR_SHIFT_LENGTH 15 /* Frame length */
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#define U8500_I2C_MCR_SHIFT_A10 1 /* Enable 10 bit address */
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#define U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP 0
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/* Status Register */
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/* Mask values for Status register */
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#define U8500_I2C_SR_OP 0x00000003 /* Operation */
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#define U8500_I2C_SR_STATUS 0x0000000C /* Controller Status */
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#define U8500_I2C_SR_CAUSE 0x00000070 /* Abort Cause */
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#define U8500_I2C_SR_TYPE 0x00000180 /* Receive Type */
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#define U8500_I2C_SR_LENGTH 0x000FF700 /* Transfer length */
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/* Shift values for Status register */
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#define U8500_I2C_SR_SHIFT_OP 0 /* Operation */
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#define U8500_I2C_SR_SHIFT_STATUS 2 /* Controller Status */
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#define U8500_I2C_SR_SHIFT_CAUSE 4 /* Abort Cause */
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#define U8500_I2C_SR_SHIFT_TYPE 7 /* Receive Type */
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#define U8500_I2C_SR_SHIFT_LENGTH 9 /* Transfer length */
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/* abort cause */
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#define U8500_I2C_NACK_ADDR 0
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#define U8500_I2C_NACK_DATA 1
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#define U8500_I2C_ACK_MCODE 2
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#define U8500_I2C_ARB_LOST 3
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#define U8500_I2C_BERR_START 4
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#define U8500_I2C_BERR_STOP 5
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#define U8500_I2C_OVFL 6
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/* Baud rate counter registers */
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/* Mask values for Baud rate counter register */
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#define U8500_I2C_BRCR_BRCNT2 0xFFFF /* Baud Rate Cntr BRCR for HS */
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#define U8500_I2C_BRCR_BRCNT1 0xFFFF0000 /* BRCR for Standard and Fast */
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/* Shift values for the Baud rate counter register */
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#define U8500_I2C_BRCR_SHIFT_BRCNT2 0
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#define U8500_I2C_BRCR_SHIFT_BRCNT1 16
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/* Interrupt Register */
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/* Mask values for Interrupt registers */
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#define U8500_I2C_INT_TXFE 0x00000001 /* Tx fifo empty */
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#define U8500_I2C_INT_TXFNE 0x00000002 /* Tx Fifo nearly empty */
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#define U8500_I2C_INT_TXFF 0x00000004 /* Tx Fifo Full */
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#define U8500_I2C_INT_TXFOVR 0x00000008 /* Tx Fifo over run */
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#define U8500_I2C_INT_RXFE 0x00000010 /* Rx Fifo Empty */
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#define U8500_I2C_INT_RXFNF 0x00000020 /* Rx Fifo nearly empty */
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#define U8500_I2C_INT_RXFF 0x00000040 /* Rx Fifo Full */
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#define U8500_I2C_INT_RFSR 0x00010000 /* Read From slave request */
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#define U8500_I2C_INT_RFSE 0x00020000 /* Read from slave empty */
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#define U8500_I2C_INT_WTSR 0x00040000 /* Write to Slave request */
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#define U8500_I2C_INT_MTD 0x00080000 /* Master Transcation Done*/
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#define U8500_I2C_INT_STD 0x00100000 /* Slave Transaction Done */
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#define U8500_I2C_INT_MAL 0x01000000 /* Master Arbitation Lost */
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#define U8500_I2C_INT_BERR 0x02000000 /* Bus Error */
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#define U8500_I2C_INT_MTDWS 0x10000000 /* Master Tran Done wo/ Stop */
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/* Max clocks (Hz) */
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#define U8500_I2C_MAX_STANDARD_SCL 100000
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#define U8500_I2C_MAX_FAST_SCL 400000
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#define U8500_I2C_MAX_HIGH_SPEED_SCL 3400000
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#endif /* _U8500_I2C_H_ */
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