mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
33685372cf
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
113 lines
3.5 KiB
C
113 lines
3.5 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun8i-r40-ccu.h>
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#include <dt-bindings/reset/sun8i-r40-ccu.h>
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static struct ccu_clk_gate r40_gates[] = {
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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[CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
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[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
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[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
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[CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
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[CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
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[CLK_BUS_OTG] = GATE(0x060, BIT(25)),
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[CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
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[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
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[CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
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[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
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[CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
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[CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
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[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
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[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
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[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
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[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
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[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
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[CLK_BUS_UART5] = GATE(0x06c, BIT(21)),
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[CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
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[CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
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[CLK_SPI0] = GATE(0x0a0, BIT(31)),
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[CLK_SPI1] = GATE(0x0a4, BIT(31)),
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[CLK_SPI2] = GATE(0x0a8, BIT(31)),
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[CLK_SPI3] = GATE(0x0ac, BIT(31)),
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[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
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[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
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[CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
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[CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
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};
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static struct ccu_reset r40_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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[RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
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[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
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[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
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[RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
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[RST_BUS_SPI3] = RESET(0x2c0, BIT(23)),
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[RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
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[RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
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[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
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[RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)),
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[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
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[RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
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[RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
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[RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
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[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
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[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
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[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
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[RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
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[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
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[RST_BUS_UART5] = RESET(0x2d8, BIT(21)),
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[RST_BUS_UART6] = RESET(0x2d8, BIT(22)),
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[RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
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};
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static const struct ccu_desc r40_ccu_desc = {
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.gates = r40_gates,
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.resets = r40_resets,
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};
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static int r40_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
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}
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static const struct udevice_id r40_clk_ids[] = {
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{ .compatible = "allwinner,sun8i-r40-ccu",
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.data = (ulong)&r40_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun8i_r40) = {
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.name = "sun8i_r40_ccu",
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.id = UCLASS_CLK,
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.of_match = r40_clk_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = r40_clk_bind,
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};
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