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https://github.com/AsahiLinux/u-boot
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a078c65172
This patch adds the DT nodes for the Octeon clock support via the common clk_ API. Signed-off-by: Stefan Roese <sr@denx.de>
106 lines
2.1 KiB
Text
106 lines
2.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell / Cavium Inc. EVB CN7300
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*/
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/dts-v1/;
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#include "mrvl,cn73xx.dtsi"
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/ {
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model = "cavium,ebb7304";
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compatible = "cavium,ebb7304";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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&bootbus {
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/*
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* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
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* as the initial size is too small for the 8MiB flash device
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*/
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ranges = <0 0 0 0x1f400000 0xc00000>,
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<1 0 0x10000 0x10000000 0>,
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<2 0 0x10000 0x20000000 0>,
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<3 0 0x10000 0x30000000 0>,
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<4 0 0 0x1d020000 0x10000>,
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<5 0 0x10000 0x50000000 0>,
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<6 0 0x10000 0x60000000 0>,
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<7 0 0x10000 0x70000000 0>;
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cavium,cs-config@0 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <0>;
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cavium,t-adr = <10>;
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cavium,t-ce = <50>;
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cavium,t-oe = <50>;
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cavium,t-we = <35>;
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cavium,t-rd-hld = <25>;
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cavium,t-wr-hld = <35>;
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cavium,t-pause = <0>;
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cavium,t-wait = <50>;
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cavium,t-page = <30>;
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cavium,t-rd-dly = <0>;
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cavium,page-mode = <1>;
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cavium,pages = <8>;
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cavium,bus-width = <8>;
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};
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cavium,cs-config@4 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <4>;
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cavium,t-adr = <10>;
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cavium,t-ce = <10>;
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cavium,t-oe = <160>;
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cavium,t-we = <100>;
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cavium,t-rd-hld = <10>;
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cavium,t-wr-hld = <0>;
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cavium,t-pause = <50>;
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cavium,t-wait = <50>;
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cavium,t-page = <10>;
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cavium,t-rd-dly = <10>;
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cavium,pages = <0>;
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cavium,bus-width = <8>;
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};
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flash0: nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0 0x340000>;
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read-only;
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};
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partition@300000 {
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label = "storage";
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reg = <0x340000 0x4be000>;
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};
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partition@7fe000 {
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label = "environment";
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reg = <0x7fe000 0x2000>;
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read-only;
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};
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};
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};
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&uart0 {
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clock-frequency = <1200000000>;
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};
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&i2c0 {
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u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
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clock-frequency = <100000>;
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};
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&i2c1 {
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u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
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clock-frequency = <100000>;
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};
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