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https://github.com/AsahiLinux/u-boot
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101a769d75
Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
73 lines
2.6 KiB
C
73 lines
2.6 KiB
C
/*
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* Copyright (C) 2009 ST-Ericsson SA
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*
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* Copied from the Linux version:
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* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __MACH_PRCMU_FW_V1_H
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#define __MACH_PRCMU_FW_V1_H
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#define AP_EXECUTE 2
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#define I2CREAD 1
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#define I2C_WR_OK 1
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#define I2C_RD_OK 2
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#define I2CWRITE 0
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#define PRCMU_BASE U8500_PRCMU_BASE
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#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
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#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
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#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
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#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
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#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
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#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
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#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
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#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
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#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
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#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
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#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
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#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
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#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
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#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
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#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
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#define PRCM_TCR (PRCMU_BASE + 0x1C8)
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#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
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#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
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#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
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/* Mailbox 5 Requests */
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#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
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#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
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#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2)
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#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3)
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/* Mailbox 5 ACKs */
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#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1)
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#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2)
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#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3)
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#define LOW_POWER_WAKEUP 1
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#define EXE_WAKEUP 0
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#define REQ_MB5 5
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extern int prcmu_i2c_read(u8 reg, u16 slave);
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extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
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void u8500_prcmu_enable(u32 *reg);
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void db8500_prcmu_init(void);
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#endif /* __MACH_PRCMU_FW_V1_H */
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