mirror of
https://github.com/AsahiLinux/u-boot
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a187559e3d
Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
184 lines
4.6 KiB
C
184 lines
4.6 KiB
C
/*
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* Copyright (C) 2015, Savoir-faire Linux Inc.
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*
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* Derived from MX51EVK code by
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* Guennadi Liakhovetski <lg@denx.de>
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* Freescale Semiconductor, Inc.
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*
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* Configuration settings for the TS4800 Board
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_MX51
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_OF_LIBFDT
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#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
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/* text base address used when linking */
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#define CONFIG_SYS_TEXT_BASE 0x90008000
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#include <asm/arch/imx-regs.h>
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_MXC_GPIO
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/*
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* SPI Configs
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* */
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#define CONFIG_HARD_SPI /* puts SPI: ready */
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#define CONFIG_MXC_SPI /* driver for the SPI controllers*/
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#define CONFIG_CMD_SPI /* SPI serial bus support */
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/*
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* MMC Configs
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* */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/*
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* Eth Configs
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*/
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#define CONFIG_MII
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
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#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
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#define CONFIG_BAUDRATE 115200
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/***********************************************************
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* Command definition
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***********************************************************/
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#define CONFIG_CMD_BOOTZ
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#undef CONFIG_CMD_IMLS
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/* Environment variables */
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=uImage\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
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"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs addtty; " \
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"bootm; "
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"fi; " \
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"fi; " \
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"fi; "
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_CMDLINE_EDITING
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Low level init */
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#define CONFIG_SYS_DDR_CLKSEL 0
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#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
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#define CONFIG_SYS_MAIN_PWR_ON
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/*-----------------------------------------------------------------------
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* Environment organization
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*/
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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