mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
148 lines
3.4 KiB
C
148 lines
3.4 KiB
C
/*
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* (C) Copyright 2001-2004
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#include <sja1000.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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/*
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* generate a short spike on the CAN tx line
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* to bring the couplers in sync
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*/
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void init_coupler(u32 addr)
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{
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struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr;
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/* reset */
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out_8(&ctrl->cr, CR_RR);
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/* dominant */
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out_8(&ctrl->btr0, 0x00); /* btr setup is required */
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out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */
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out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 |
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OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1);
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out_8(&ctrl->cr, 0x00);
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/* delay */
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in_8(&ctrl->cr);
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in_8(&ctrl->cr);
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in_8(&ctrl->cr);
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in_8(&ctrl->cr);
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/* reset */
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out_8(&ctrl->cr, CR_RR);
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}
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
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/*
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* Reset CPLD via GPIO12 (CS3) pin
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*/
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 12));
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udelay(1000); /* wait 1ms */
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) | (0x80000000 >> 12));
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udelay(1000); /* wait 1ms */
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return 0;
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}
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Init magnetic coupler
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*/
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if (!getenv("noinitcoupler"))
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init_coupler(CAN_BA);
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_f("serial#", str, sizeof(str));
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int flashcnt;
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int delay;
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u8 *led_reg = (u8 *)(CAN_BA + 0x1000);
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming VOM405");
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} else {
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puts(str);
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}
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printf(" (PLD-Version=%02d)\n", in_8(led_reg));
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/*
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* Flash LEDs
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*/
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for (flashcnt = 0; flashcnt < 3; flashcnt++) {
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out_8(led_reg, 0x40); /* LED_B..D off */
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for (delay = 0; delay < 100; delay++)
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udelay(1000);
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out_8(led_reg, 0x47); /* LED_B..D on */
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for (delay = 0; delay < 50; delay++)
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udelay(1000);
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}
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out_8(led_reg, 0x40);
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return 0;
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}
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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