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bbfb81c187
The startup code in arm/cpu/arm926ejs preserves the link register across the call to lowlevel_init by using r4: mov r4, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ mov lr, r4 /* restore link */ The lowlevel_init function for at91 machines based on the same CPU uses r4 and hence corrupts it causing a data abort when it returns to the startup code. This patch fixes this by using r6 instead of r4 in the lowlevel_init function. Discovered and the fix was tested on a AT91SAM9261 based board. Signed-off-by: Martin Townsend <martin@rufilla.com> Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
245 lines
6.3 KiB
ArmAsm
245 lines
6.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*/
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#include <config.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_wdt.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91sam9_sdramc.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_rstc.h>
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#ifdef CONFIG_ATMEL_LEGACY
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#include <asm/arch/at91sam9_matrix.h>
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#endif
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#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
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#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
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#endif
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.globl lowlevel_init
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.type lowlevel_init,function
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lowlevel_init:
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POS1:
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adr r5, POS1 /* r5 = POS1 run time */
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ldr r0, =POS1 /* r0 = POS1 compile */
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sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
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/* memory control configuration 1 */
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ldr r0, =SMRDATA
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ldr r2, =SMRDATA1
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add r0, r0, r5
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add r2, r2, r5
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0:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 0b
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/* ----------------------------------------------------------------------------
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* PMC Init Step 1.
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* ----------------------------------------------------------------------------
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* - Check if the PLL is already initialized
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* ----------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_ASM_PMC_MCKR)
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ldr r0, [r1]
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and r0, r0, #3
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cmp r0, #0
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bne PLL_setup_end
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/* ---------------------------------------------------------------------------
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* - Enable the Main Oscillator
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* ---------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_ASM_PMC_MOR)
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ldr r2, =(AT91_ASM_PMC_SR)
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/* Main oscillator Enable register PMC_MOR: */
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ldr r0, =CONFIG_SYS_MOR_VAL
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str r0, [r1]
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/* Reading the PMC Status to detect when the Main Oscillator is enabled */
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mov r6, #AT91_PMC_IXR_MOSCS
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MOSCS_Loop:
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ldr r3, [r2]
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and r3, r6, r3
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cmp r3, #AT91_PMC_IXR_MOSCS
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bne MOSCS_Loop
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/* ----------------------------------------------------------------------------
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* PMC Init Step 2.
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* ----------------------------------------------------------------------------
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* Setup PLLA
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* ----------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_ASM_PMC_PLLAR)
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ldr r0, =CONFIG_SYS_PLLAR_VAL
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str r0, [r1]
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/* Reading the PMC Status register to detect when the PLLA is locked */
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mov r6, #AT91_PMC_IXR_LOCKA
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MOSCS_Loop1:
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ldr r3, [r2]
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and r3, r6, r3
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cmp r3, #AT91_PMC_IXR_LOCKA
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bne MOSCS_Loop1
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/* ----------------------------------------------------------------------------
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* PMC Init Step 3.
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* ----------------------------------------------------------------------------
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* - Switch on the Main Oscillator
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* ----------------------------------------------------------------------------
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*/
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ldr r1, =(AT91_ASM_PMC_MCKR)
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/* -Master Clock Controller register PMC_MCKR */
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ldr r0, =CONFIG_SYS_MCKR1_VAL
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str r0, [r1]
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/* Reading the PMC Status to detect when the Master clock is ready */
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mov r6, #AT91_PMC_IXR_MCKRDY
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MCKRDY_Loop:
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ldr r3, [r2]
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and r3, r6, r3
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cmp r3, #AT91_PMC_IXR_MCKRDY
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bne MCKRDY_Loop
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ldr r0, =CONFIG_SYS_MCKR2_VAL
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str r0, [r1]
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/* Reading the PMC Status to detect when the Master clock is ready */
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mov r6, #AT91_PMC_IXR_MCKRDY
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MCKRDY_Loop1:
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ldr r3, [r2]
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and r3, r6, r3
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cmp r3, #AT91_PMC_IXR_MCKRDY
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bne MCKRDY_Loop1
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PLL_setup_end:
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/* ----------------------------------------------------------------------------
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* - memory control configuration 2
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* ----------------------------------------------------------------------------
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*/
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ldr r0, =(AT91_ASM_SDRAMC_TR)
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ldr r1, [r0]
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cmp r1, #0
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bne SDRAM_setup_end
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ldr r0, =SMRDATA1
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ldr r2, =SMRDATA2
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add r0, r0, r5
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add r2, r2, r5
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2:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 2b
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SDRAM_setup_end:
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/* everything is fine now */
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mov pc, lr
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.ltorg
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SMRDATA:
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.word AT91_ASM_WDT_MR
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.word CONFIG_SYS_WDTC_WDMR_VAL
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/* configure PIOx as EBI0 D[16-31] */
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#if defined(CONFIG_AT91SAM9263)
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.word AT91_ASM_PIOD_PDR
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.word CONFIG_SYS_PIOD_PDR_VAL1
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.word AT91_ASM_PIOD_PUDR
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.word CONFIG_SYS_PIOD_PPUDR_VAL
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.word AT91_ASM_PIOD_ASR
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.word CONFIG_SYS_PIOD_PPUDR_VAL
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#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
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|| defined(CONFIG_AT91SAM9G20)
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.word AT91_ASM_PIOC_PDR
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.word CONFIG_SYS_PIOC_PDR_VAL1
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.word AT91_ASM_PIOC_PUDR
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.word CONFIG_SYS_PIOC_PPUDR_VAL
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#endif
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.word AT91_ASM_MATRIX_CSA0
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.word CONFIG_SYS_MATRIX_EBICSA_VAL
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/* flash */
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.word AT91_ASM_SMC_MODE0
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.word CONFIG_SYS_SMC0_MODE0_VAL
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.word AT91_ASM_SMC_CYCLE0
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.word CONFIG_SYS_SMC0_CYCLE0_VAL
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.word AT91_ASM_SMC_PULSE0
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.word CONFIG_SYS_SMC0_PULSE0_VAL
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.word AT91_ASM_SMC_SETUP0
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.word CONFIG_SYS_SMC0_SETUP0_VAL
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SMRDATA1:
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.word AT91_ASM_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL1
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.word AT91_ASM_SDRAMC_TR
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.word CONFIG_SYS_SDRC_TR_VAL1
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.word AT91_ASM_SDRAMC_CR
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.word CONFIG_SYS_SDRC_CR_VAL
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.word AT91_ASM_SDRAMC_MDR
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.word CONFIG_SYS_SDRC_MDR_VAL
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.word AT91_ASM_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL2
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL1
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.word AT91_ASM_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL3
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL2
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL3
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL4
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL5
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL6
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL7
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL8
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL9
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.word AT91_ASM_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL4
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL10
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.word AT91_ASM_SDRAMC_MR
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.word CONFIG_SYS_SDRC_MR_VAL5
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL11
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.word AT91_ASM_SDRAMC_TR
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.word CONFIG_SYS_SDRC_TR_VAL2
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.word CONFIG_SYS_SDRAM_BASE
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.word CONFIG_SYS_SDRAM_VAL12
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/* User reset enable*/
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.word AT91_ASM_RSTC_MR
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.word CONFIG_SYS_RSTC_RMR_VAL
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#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
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/* MATRIX_MCFG - REMAP all masters */
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.word AT91_ASM_MATRIX_MCFG
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.word 0x1FF
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#endif
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SMRDATA2:
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.word 0
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