mirror of
https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
110 lines
3.3 KiB
C
110 lines
3.3 KiB
C
/*
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* (C) Copyright 2001
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* Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* 74xx_7xx.h
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*
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* 74xx/7xx specific definitions
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*/
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#ifndef __MPC74XX_H__
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#define __MPC74XX_H__
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/*----------------------------------------------------------------
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* Exception offsets (PowerPC standard)
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*/
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#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
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#define _START_OFFSET EXC_OFF_SYS_RESET
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/*----------------------------------------------------------------
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* l2cr values
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*/
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#define l2cr 1017
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#define L2CR_L2E 0x80000000 /* bit 0 - enable */
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#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
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#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
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#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
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#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
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#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
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#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
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#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
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#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
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#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
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#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
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#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
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#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
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#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
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#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
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#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
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#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
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#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
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#define L2CR_TS 0x00040000 /* bit 13 - test support on */
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#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
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#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
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#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
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#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
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#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
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#ifndef __ASSEMBLY__
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/* cpu ids we detect */
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typedef enum __cpu_t {
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CPU_740, CPU_750,
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CPU_740P, CPU_750P,
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CPU_745, CPU_755,
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CPU_750CX, CPU_750FX, CPU_750GX,
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CPU_7400,
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CPU_7410,
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CPU_7447A, CPU_7448,
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CPU_7450, CPU_7455, CPU_7457,
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CPU_UNKNOWN} cpu_t;
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extern cpu_t get_cpu_type(void);
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#define l1icache_enable icache_enable
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void l2cache_enable(void);
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void l1dcache_enable(void);
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static __inline__ unsigned long get_msr (void)
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{
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unsigned long msr;
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asm volatile("mfmsr %0" : "=r" (msr) :);
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return msr;
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}
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static __inline__ void set_msr (unsigned long msr)
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{
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asm volatile("mtmsr %0" : : "r" (msr));
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}
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static __inline__ unsigned long get_hid0 (void)
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{
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unsigned long hid0;
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asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
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return hid0;
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}
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static __inline__ unsigned long get_hid1 (void)
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{
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unsigned long hid1;
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asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
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return hid1;
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}
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static __inline__ void set_hid0 (unsigned long hid0)
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{
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asm volatile("mtspr 1008, %0" : : "r" (hid0));
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}
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static __inline__ void set_hid1 (unsigned long hid1)
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{
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asm volatile("mtspr 1009, %0" : : "r" (hid1));
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __MPC74XX_H__ */
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