mirror of
https://github.com/AsahiLinux/u-boot
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9fbdb1aac5
Do not hardcode the ipu_clk frequency and let the board file pass this value. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
257 lines
6.7 KiB
C
257 lines
6.7 KiB
C
/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the MX51EVK Board
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_MX51 /* in a mx51 */
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#define CONFIG_SYS_MX5_HCLK 24000000
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#define CONFIG_SYS_MX5_CLK32 32768
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TEXT_BASE 0x97800000
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#include <asm/arch/imx-regs.h>
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/*
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* Disabled for now due to build problems under Debian and a significant
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* increase in the final file size: 144260 vs. 109536 Bytes.
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*/
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_OF_LIBFDT
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#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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#define CONFIG_BOARD_LATE_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_MXC_GPIO
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/*
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* SPI Configs
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* */
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#define CONFIG_CMD_SPI
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#define CONFIG_MXC_SPI
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/* PMIC Controller */
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#define CONFIG_PMIC
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#define CONFIG_PMIC_SPI
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#define CONFIG_PMIC_FSL
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#define CONFIG_FSL_PMIC_BUS 0
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 2500000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/*
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* MMC Configs
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* */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 2
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/*
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* Eth Configs
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*/
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#define CONFIG_HAS_ETH1
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#define CONFIG_MII
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#define CONFIG_DISCOVER_PHY
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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/* USB Configs */
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_FAT
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX5
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_ETHER_SMSC95XX
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#define CONFIG_MXC_USB_PORT 1
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#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
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#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
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/* Framebuffer and LCD */
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#define CONFIG_PREBOOT
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_IPUV3
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_IPUV3_CLK 133000000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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/***********************************************************
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* Command definition
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***********************************************************/
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_DATE
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_ETHPRIME "FEC0"
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#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"uimage=uImage\0" \
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"mmcdev=0\0" \
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"mmcpart=2\0" \
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"mmcroot=/dev/mmcblk0p3 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm\0" \
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"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"dhcp ${uimage}; bootm\0" \
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#define CONFIG_BOOTCOMMAND \
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"if mmc rescan ${mmcdev}; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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#define CONFIG_ARP_TIMEOUT 200UL
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > "
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x90000000
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#define CONFIG_SYS_MEMTEST_END 0x90010000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_CMDLINE_EDITING
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_SYS_DDR_CLKSEL 0
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#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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