mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 16:39:35 +00:00
338 lines
9.4 KiB
C
338 lines
9.4 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Copied from lubbock.h
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*
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* (C) Copyright 2004
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* BEC Systems <http://bec-systems.com>
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* Cliff Brake <cliff.brake@gmail.com>
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* Configuation settings for the Accelent/Vibren PXA255 IDP
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/pxa-regs.h>
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/*
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* If we are developing, we might want to start armboot from ram
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* so we MUST NOT initialize critical regs like mem-timing ...
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*/
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#define CONFIG_INIT_CRITICAL /* undef for developing */
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/*
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* define the following to enable debug blinks. A debug blink function
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* must be defined in memsetup.S
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*/
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#undef DEBUG_BLINK_ENABLE
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#undef DEBUG_BLINKC_ENABLE
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
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#undef CONFIG_LCD
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#ifdef CONFIG_LCD
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#define CONFIG_SHARP_LM8V31
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#endif
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#define CONFIG_MMC 1
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#define BOARD_LATE_INIT 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/*
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* Size of malloc() pool
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*/
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#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/*
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* PXA250 IDP memory map information
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*/
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#define IDP_CS5_ETH_OFFSET 0x03400000
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/*
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* Hardware drivers
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*/
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#define CONFIG_DRIVER_SMC91111
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#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
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#define CONFIG_SMC_USE_32_BIT 1
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/* #define CONFIG_SMC_USE_IOFUNCS */
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/* the following has to be set high -- suspect something is wrong with
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* with the tftp timeout routines. FIXME!!!
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*/
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#define CONFIG_NET_RETRY_COUNT 100
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/*
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* select serial console configuration
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*/
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#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTCOMMAND "bootm 40000"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
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#define CONFIG_CMDLINE_TAG
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/*
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* Current memory map for Vibren supplied Linux images:
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*
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* Flash:
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* 0 - 0x3ffff (size = 0x40000): bootloader
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* 0x40000 - 0x13ffff (size = 0x100000): kernel
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* 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
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*
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* RAM:
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* 0xa0008000 - kernel is loaded
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* 0xa3000000 - Uboot runs (48MB into RAM)
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*
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"prog_boot_mmc=" \
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"mw.b 0xa0000000 0xff 0x40000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0000000 u-boot.bin; " \
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"then " \
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"protect off 0x0 0x3ffff; " \
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"erase 0x0 0x3ffff; " \
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"cp.b 0xa0000000 0x0 0x40000; " \
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"reset;" \
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"fi\0" \
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"prog_uzImage_mmc=" \
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"mw.b 0xa0000000 0xff 0x100000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0000000 uzImage; " \
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"then " \
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"protect off 0x40000 0xfffff; " \
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"erase 0x40000 0xfffff; " \
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"cp.b 0xa0000000 0x40000 0x100000; " \
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"fi\0" \
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"prog_jffs_mmc=" \
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"mw.b 0xa0000000 0xff 0x1e00000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0000000 root.jffs; " \
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"then " \
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"protect off 0x140000 0x1f3ffff; " \
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"erase 0x140000 0x1f3ffff; " \
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"cp.b 0xa0000000 0x140000 0x1e00000; " \
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"fi\0" \
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"boot_mmc=" \
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"if mmcinit && " \
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"fatload mmc 0 0xa1000000 uzImage && " \
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"then " \
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"bootm 0xa1000000; " \
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"fi\0" \
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"prog_boot_net=" \
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"mw.b 0xa0000000 0xff 0x100000; " \
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"if bootp 0xa0000000 u-boot.bin; " \
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"then " \
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"protect off 0x0 0x3ffff; " \
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"erase 0x0 0x3ffff; " \
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"cp.b 0xa0000000 0x0 0x40000; " \
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"reset; " \
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"fi\0" \
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"prog_uzImage_net=" \
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"mw.b 0xa0000000 0xff 0x100000; " \
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"if bootp 0xa0000000 uzImage; " \
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"then " \
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"protect off 0x40000 0xfffff; " \
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"erase 0x40000 0xfffff; " \
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"cp.b 0xa0000000 0x40000 0x100000; " \
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"fi\0" \
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"prog_jffs_net=" \
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"mw.b 0xa0000000 0xff 0x1e00000; " \
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"if bootp 0xa0000000 root.jffs; " \
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"then " \
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"protect off 0x140000 0x1f3ffff; " \
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"erase 0x140000 0x1f3ffff; " \
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"cp.b 0xa0000000 0x140000 0x1e00000; " \
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"fi\0"
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/* "erase_env=" */
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/* "protect off" */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HUSH_PARSER 1
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CFG_LONGHELP /* undef to save memory */
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#endif
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_DEVICE_NULLDEV 1
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#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#define CFG_LOAD_ADDR 0xa0800000 /* default load address */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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#define RTC 1 /* enable 32KHz osc */
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/* valid baudrates */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_MMC_BASE 0xF0000000
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/*
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
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#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
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#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
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#define CFG_DRAM_BASE 0xa0000000
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#define CFG_DRAM_SIZE 0x04000000
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#define CFG_FLASH_BASE PHYS_FLASH_1
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/*
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* GPIO settings
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*/
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#define CFG_GAFR0_L_VAL 0x80001005
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#define CFG_GAFR0_U_VAL 0xa5128012
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#define CFG_GAFR1_L_VAL 0x699a9558
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#define CFG_GAFR1_U_VAL 0xaaa5aa6a
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#define CFG_GAFR2_L_VAL 0xaaaaaaaa
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#define CFG_GAFR2_U_VAL 0x2
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#define CFG_GPCR0_VAL 0x1800400
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#define CFG_GPCR1_VAL 0x0
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#define CFG_GPCR2_VAL 0x0
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#define CFG_GPDR0_VAL 0xc1818440
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#define CFG_GPDR1_VAL 0xfcffab82
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#define CFG_GPDR2_VAL 0x1ffff
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#define CFG_GPSR0_VAL 0x8000
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#define CFG_GPSR1_VAL 0x3f0002
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#define CFG_GPSR2_VAL 0x1c000
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#define CFG_PSSR_VAL 0x20
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/*
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* Memory settings
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*/
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#define CFG_MSC0_VAL 0x29DCA4D2
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#define CFG_MSC1_VAL 0x43AC494C
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#define CFG_MSC2_VAL 0x39D449D4
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#define CFG_MDCNFG_VAL 0x090009C9
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#define CFG_MDREFR_VAL 0x0085C017
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#define CFG_MDMRS_VAL 0x00220022
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/*
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* PCMCIA and CF Interfaces
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*/
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#define CFG_MECR_VAL 0x00000003
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#define CFG_MCMEM0_VAL 0x00014405
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#define CFG_MCMEM1_VAL 0x00014405
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#define CFG_MCATT0_VAL 0x00014405
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#define CFG_MCATT1_VAL 0x00014405
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#define CFG_MCIO0_VAL 0x00014405
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#define CFG_MCIO1_VAL 0x00014405
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/*
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* FLASH and environment organization
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*/
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#define CFG_FLASH_CFI
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#define CFG_FLASH_CFI_DRIVER 1
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#define CFG_MONITOR_BASE 0
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#define CFG_MONITOR_LEN 0x40000
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CFG_FLASH_USE_BUFFER_WRITE 1
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/* timeout values are in ticks */
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#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
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/* put cfg at end of flash for now */
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#define CFG_ENV_IS_IN_FLASH 1
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/* Addr of Environment Sector */
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#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
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#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x40000
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#endif /* __CONFIG_H */
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