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0a137ac501
Some SoCs of the H616 family use a die variant, that puts some CPU power and reset control registers at a different address. There are examples of two instances of the same board, using different die revisions of the otherwise same H313 SoC. We need to write to a register in that block *very* early in the SPL boot, to switch the core to AArch64. Since the devices are otherwise indistinguishable, let the SPL code read that die variant and use the respective RVBAR address based on that. That is a bit tricky, since we need to do that in hand-coded AArch32 machine language, shared by all 64-bit SoCs. To avoid build dependencies in this mess, we always provide two addresses to choose from, and just give identical values for all other SoCs. This allows the same code to run on all 64-bit SoCs, and controls this switch behaviour purely from Kconfig. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> |
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| .. | ||
| dram_timings | ||
| board.c | ||
| clock.c | ||
| clock_sun4i.c | ||
| clock_sun6i.c | ||
| clock_sun8i_a83t.c | ||
| clock_sun9i.c | ||
| clock_sun50i_h6.c | ||
| cpu_info.c | ||
| dram_helpers.c | ||
| dram_sun4i.c | ||
| dram_sun6i.c | ||
| dram_sun8i_a23.c | ||
| dram_sun8i_a33.c | ||
| dram_sun8i_a83t.c | ||
| dram_sun9i.c | ||
| dram_sun50i_h6.c | ||
| dram_sun50i_h616.c | ||
| dram_suniv.c | ||
| dram_sunxi_dw.c | ||
| gtbus_sun9i.c | ||
| Kconfig | ||
| Makefile | ||
| pinmux.c | ||
| pmic_bus.c | ||
| prcm.c | ||
| rmr_switch.S | ||
| spl_spi_sunxi.c | ||
| timer.c | ||