mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-12 16:07:30 +00:00
a509161a21
The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
17 lines
336 B
ArmAsm
17 lines
336 B
ArmAsm
/*
|
|
* Copyright (C) 2015 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <linux/linkage.h>
|
|
#include <mach/ssc-regs.h>
|
|
|
|
ENTRY(lowlevel_init)
|
|
ldr r1, = SSCC
|
|
ldr r0, [r1]
|
|
bic r0, r0, #SSCC_ON @ L2 disable
|
|
str r0, [r1]
|
|
mov pc, lr
|
|
ENDPROC(lowlevel_init)
|