mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
4549e789c1
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have multiple licenses (in these cases, dual license) declared in the SPDX-License-Identifier tag. In this case we change from listing "LICENSE-A LICENSE-B" or "LICENSE-A or LICENSE-B" or "(LICENSE-A OR LICENSE-B)" to "LICENSE-A OR LICENSE-B" as per the Linux Kernel style document. Note that parenthesis are allowed so when they were used before we continue to use them. Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
151 lines
4.6 KiB
Text
151 lines
4.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Freescale ls2080a SOC common device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*/
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/ {
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compatible = "fsl,ls2080a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>;
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/* DRAM space - 1, size : 2 GB DRAM */
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};
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <1 9 0x4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
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<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
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<1 11 0x8>, /* Virtual PPI, active-low */
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<1 10 0x8>; /* Hypervisor PPI, active-low */
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};
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serial0: serial@21c0500 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0500 0x0 0x100>;
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clock-frequency = <0>; /* Updated by bootloader */
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interrupts = <0 32 0x1>; /* edge triggered */
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};
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serial1: serial@21c0600 {
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550a";
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reg = <0x0 0x21c0600 0x0 0x100>;
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clock-frequency = <0>; /* Updated by bootloader */
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interrupts = <0 32 0x1>; /* edge triggered */
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};
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fsl_mc: fsl-mc@80c000000 {
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compatible = "fsl,qoriq-mc";
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reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
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<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
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};
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dspi: dspi@2100000 {
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compatible = "fsl,vf610-dspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x2100000 0x0 0x10000>;
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interrupts = <0 26 0x4>; /* Level high type */
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num-cs = <6>;
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};
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qspi: quadspi@1550000 {
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compatible = "fsl,vf610-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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num-cs = <4>;
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};
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usb0: usb3@3100000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3100000 0x0 0x10000>;
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interrupts = <0 80 0x4>; /* Level high type */
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dr_mode = "host";
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};
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usb1: usb3@3110000 {
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compatible = "fsl,layerscape-dwc3";
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reg = <0x0 0x3110000 0x0 0x10000>;
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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};
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pcie@3400000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
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0x00 0x03480000 0x0 0x80000 /* lut registers */
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0x10 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3500000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
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0x00 0x03580000 0x0 0x80000 /* lut registers */
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0x12 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3600000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
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0x00 0x03680000 0x0 0x80000 /* lut registers */
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0x14 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <8>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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pcie@3700000 {
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compatible = "fsl,ls-pcie", "snps,dw-pcie";
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reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
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0x00 0x03780000 0x0 0x80000 /* lut registers */
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0x16 0x00000000 0x0 0x20000>; /* configuration space */
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reg-names = "dbi", "lut", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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};
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