mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-29 02:42:16 +00:00
0ed384fd2f
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
315 lines
9.9 KiB
C
315 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2019, 2021 NXP
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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#define DDR_SDRAM_CFG 0x470c0008
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#define DDR_CS0_BNDS 0x008000bf
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#define DDR_CS0_CONFIG 0x80014302
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#define DDR_TIMING_CFG_0 0x50550004
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#define DDR_TIMING_CFG_1 0xbcb38c56
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#define DDR_TIMING_CFG_2 0x0040d120
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#define DDR_TIMING_CFG_3 0x010e1000
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#define DDR_TIMING_CFG_4 0x00000001
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#define DDR_TIMING_CFG_5 0x03401400
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#define DDR_SDRAM_CFG_2 0x00401010
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#define DDR_SDRAM_MODE 0x00061c60
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#define DDR_SDRAM_MODE_2 0x00180000
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#define DDR_SDRAM_INTERVAL 0x18600618
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#define DDR_DDR_WRLVL_CNTL 0x8655f605
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#define DDR_DDR_WRLVL_CNTL_2 0x05060607
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#define DDR_DDR_WRLVL_CNTL_3 0x05050505
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#define DDR_DDR_CDR1 0x80040000
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#define DDR_DDR_CDR2 0x00000001
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#define DDR_SDRAM_CLK_CNTL 0x02000000
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#define DDR_DDR_ZQ_CNTL 0x89080600
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#define DDR_CS0_CONFIG_2 0
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#define DDR_SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
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#define SDRAM_CFG2_FRC_SR 0x80000000
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#define SDRAM_CFG_BI 0x00000001
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#ifdef CONFIG_SD_BOOT
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#ifdef CONFIG_NXP_ESBC
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image.
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*/
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#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
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#endif /* ifdef CONFIG_NXP_ESBC */
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#ifdef CONFIG_U_BOOT_HDR_SIZE
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/*
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* HDR would be appended at end of image and copied to DDR along
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* with U-Boot image. Here u-boot max. size is 512K. So if binary
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* size increases then increase this size in case of secure boot as
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* it uses raw u-boot image instead of fit image.
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*/
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#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
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#endif
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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/*
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* IFC Definitions
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*/
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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/* NOR Flash Timing Params */
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#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TAVDS(0x0) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1A) | \
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWP(0x1c) | \
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FTIM2_NOR_TWPH(0x0e))
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#define CFG_SYS_NOR_FTIM3 0
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#endif
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/* CPLD */
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#define CONFIG_SYS_CPLD_BASE 0x7fb00000
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#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
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#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
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#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/* CPLD Timing parameters for IFC GPCM */
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#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
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FTIM0_GPCM_TEADC(0xf) | \
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FTIM0_GPCM_TEAHC(0xf))
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#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0xff))
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#define CONFIG_SYS_FPGA_FTIM3 0x0
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
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/*
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* Serial Port
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*/
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#ifndef CONFIG_LPUART
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#define CONFIG_SYS_NS16550_SERIAL
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#ifndef CONFIG_DM_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#define CONFIG_SYS_NS16550_CLK get_serial_clock()
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#endif
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/*
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* I2C
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*/
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/* GPIO */
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#define CONFIG_PEN_ADDR_BIG_ENDIAN
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#define CONFIG_SMP_PEN_ADDR 0x01ee0200
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 256
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#define CONFIG_FSL_DEVICE_DISABLE
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(USB, usb, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#ifdef CONFIG_LPUART
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \
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"cma=64M@0x0-0xb0000000\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr=0x65000000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x90000000\0" \
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"ramdisk_addr_r=0xa0000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernel_size_sd=0x14000\0" \
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"othbootargs=cma=64M@0x0-0xb0000000\0" \
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BOOTENV \
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"boot_scripts=ls1021atwr_boot.scr\0" \
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"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"done;" \
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"\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr}; " \
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"env exists secureboot " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"installer=load mmc 0:2 $load_addr " \
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"/flex_installer_arm32.itb; " \
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"bootm $load_addr#ls1021atwr\0" \
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"qspi_bootcmd=echo Trying load from qspi..;" \
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"sf probe && sf read $load_addr " \
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"$kernel_addr $kernel_size && bootm $load_addr#$board\0" \
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"nor_bootcmd=echo Trying load from nor..;" \
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"cp.b $kernel_addr $load_addr " \
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"$kernel_size && bootm $load_addr#$board\0"
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#else
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \
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"cma=64M@0x0-0xb0000000\0" \
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"initrd_high=0xffffffff\0" \
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"kernel_addr=0x61000000\0" \
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"kernelheader_addr=0x60800000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x81000000\0" \
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"kernelheader_size=0x40000\0" \
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"fdt_addr_r=0x90000000\0" \
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"ramdisk_addr_r=0xa0000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernel_size_sd=0x14000\0" \
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"kernelhdr_addr_sd=0x4000\0" \
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"kernelhdr_size_sd=0x10\0" \
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"othbootargs=cma=64M@0x0-0xb0000000\0" \
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BOOTENV \
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"boot_scripts=ls1021atwr_boot.scr\0" \
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"boot_script_hdr=hdr_ls1021atwr_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"done;" \
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"\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"qspi_bootcmd=echo Trying load from qspi..;" \
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"sf probe && sf read $load_addr " \
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"$kernel_addr $kernel_size; env exists secureboot " \
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"&& sf read $kernelheader_addr_r $kernelheader_addr " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0" \
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"nor_bootcmd=echo Trying load from nor..;" \
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"cp.b $kernel_addr $load_addr " \
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"$kernel_size; env exists secureboot " \
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"&& cp.b $kernelheader_addr $kernelheader_addr_r " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
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"bootm $load_addr#$board\0" \
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"sd_bootcmd=echo Trying load from SD ..;" \
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"mmcinfo && mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"env exists secureboot && mmc read $kernelheader_addr_r " \
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"$kernelhdr_addr_sd $kernelhdr_size_sd " \
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" && esbc_validate ${kernelheader_addr_r};" \
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"bootm $load_addr#$board\0"
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_LS102XA_STREAM_ID
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/*
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* Environment
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*/
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#include <asm/fsl_secure_boot.h>
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#endif
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