mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
937175ee72
This driver cannot work when booted from coreboot, since the FSP information is not available. Disable it in that case, so that the coreboot video driver can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
182 lines
4.3 KiB
C
182 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*/
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#define LOG_CATEGORY UCLASS_VIDEO
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#include <common.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <vbe.h>
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#include <video.h>
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#include <acpi/acpi_table.h>
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#include <asm/fsp/fsp_support.h>
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#include <asm/global_data.h>
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#include <asm/intel_opregion.h>
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#include <asm/mtrr.h>
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#include <dm/acpi.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct pixel {
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u8 pos;
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u8 size;
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};
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static const struct fsp_framebuffer {
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struct pixel red;
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struct pixel green;
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struct pixel blue;
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struct pixel rsvd;
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} fsp_framebuffer_format_map[] = {
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[pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
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[pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
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};
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static int save_vesa_mode(struct vesa_mode_info *vesa)
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{
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const struct hob_graphics_info *ginfo;
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const struct fsp_framebuffer *fbinfo;
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ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
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/*
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* If there is no graphics info structure, bail out and keep
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* running on the serial console.
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*
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* Note: on some platforms (eg: Braswell), the FSP will not produce
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* the graphics info HOB unless you plug some cables to the display
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* interface (eg: HDMI) on the board.
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*/
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if (!ginfo) {
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debug("FSP graphics hand-off block not found\n");
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return -ENXIO;
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}
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vesa->x_resolution = ginfo->width;
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vesa->y_resolution = ginfo->height;
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vesa->bits_per_pixel = 32;
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vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
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vesa->phys_base_ptr = ginfo->fb_base;
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if (ginfo->pixel_format >= pixel_bitmask) {
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debug("FSP set unknown framebuffer format: %d\n",
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ginfo->pixel_format);
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return -EINVAL;
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}
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fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
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vesa->red_mask_size = fbinfo->red.size;
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vesa->red_mask_pos = fbinfo->red.pos;
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vesa->green_mask_size = fbinfo->green.size;
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vesa->green_mask_pos = fbinfo->green.pos;
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vesa->blue_mask_size = fbinfo->blue.size;
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vesa->blue_mask_pos = fbinfo->blue.pos;
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vesa->reserved_mask_size = fbinfo->rsvd.size;
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vesa->reserved_mask_pos = fbinfo->rsvd.pos;
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return 0;
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}
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static int fsp_video_probe(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct vesa_mode_info *vesa = &mode_info.vesa;
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int ret;
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if (!ll_boot_init())
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return -ENODEV;
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printf("Video: ");
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/* Initialize vesa_mode_info structure */
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ret = save_vesa_mode(vesa);
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if (ret)
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goto err;
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/*
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* The framebuffer base address in the FSP graphics info HOB reflects
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* the value assigned by the FSP. After PCI enumeration the framebuffer
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* base address may be relocated. Let's get the updated one from device.
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*
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* For IGD, it seems to be always on BAR2.
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*/
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vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
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gd->fb_base = vesa->phys_base_ptr;
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ret = vbe_setup_video_priv(vesa, uc_priv, plat);
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if (ret)
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goto err;
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mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
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mtrr_commit(true);
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printf("%dx%dx%d @ %x\n", uc_priv->xsize, uc_priv->ysize,
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vesa->bits_per_pixel, vesa->phys_base_ptr);
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return 0;
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err:
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printf("No video mode configured in FSP!\n");
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return ret;
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}
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static int fsp_video_bind(struct udevice *dev)
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{
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struct video_uc_plat *plat = dev_get_uclass_plat(dev);
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/* Set the maximum supported resolution */
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plat->size = 2560 * 1600 * 4;
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return 0;
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}
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#ifdef CONFIG_INTEL_GMA_ACPI
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static int fsp_video_acpi_write_tables(const struct udevice *dev,
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struct acpi_ctx *ctx)
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{
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struct igd_opregion *opregion;
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int ret;
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log_debug("ACPI: * IGD OpRegion\n");
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opregion = (struct igd_opregion *)ctx->current;
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ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion);
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if (ret)
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return ret;
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acpi_inc_align(ctx, sizeof(struct igd_opregion));
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return 0;
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}
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#endif
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struct acpi_ops fsp_video_acpi_ops = {
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#ifdef CONFIG_INTEL_GMA_ACPI
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.write_tables = fsp_video_acpi_write_tables,
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#endif
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};
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static const struct udevice_id fsp_video_ids[] = {
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{ .compatible = "fsp-fb" },
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{ }
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};
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U_BOOT_DRIVER(fsp_video) = {
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.name = "fsp_video",
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.id = UCLASS_VIDEO,
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.of_match = fsp_video_ids,
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.bind = fsp_video_bind,
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.probe = fsp_video_probe,
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.flags = DM_FLAG_PRE_RELOC,
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ACPI_OPS_PTR(&fsp_video_acpi_ops)
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};
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static struct pci_device_id fsp_video_supported[] = {
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{ PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
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{ },
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};
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U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);
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