mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-15 15:53:02 +00:00
e3a7239cd0
Add ESPI controller DT node for P3041. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
149 lines
3.7 KiB
Text
149 lines
3.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* P3041 Silicon/SoC Device Tree Source (pre include)
|
|
*
|
|
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
|
|
* Copyright 2019-2020 NXP
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/include/ "e500mc_power_isa.dtsi"
|
|
|
|
/ {
|
|
compatible = "fsl,P3041";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&mpic>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: PowerPC,e500mc@0 {
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
fsl,portid-mapping = <0x80000000>;
|
|
};
|
|
cpu1: PowerPC,e500mc@1 {
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
fsl,portid-mapping = <0x40000000>;
|
|
};
|
|
cpu2: PowerPC,e500mc@2 {
|
|
device_type = "cpu";
|
|
reg = <2>;
|
|
fsl,portid-mapping = <0x20000000>;
|
|
};
|
|
cpu3: PowerPC,e500mc@3 {
|
|
device_type = "cpu";
|
|
reg = <3>;
|
|
fsl,portid-mapping = <0x10000000>;
|
|
};
|
|
};
|
|
|
|
soc: soc@ffe000000 {
|
|
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
|
reg = <0xf 0xfe000000 0 0x00001000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
device_type = "soc";
|
|
compatible = "simple-bus";
|
|
|
|
mpic: pic@40000 {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <4>;
|
|
reg = <0x40000 0x40000>;
|
|
compatible = "fsl,mpic", "chrp,open-pic";
|
|
device_type = "open-pic";
|
|
clock-frequency = <0x0>;
|
|
};
|
|
|
|
espi0: spi@110000 {
|
|
compatible = "fsl,mpc8536-espi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x110000 0x1000>;
|
|
fsl,espi-num-chipselects = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: usb@fe210000 {
|
|
compatible = "fsl-usb2-mph";
|
|
reg = <0x210000 0x1000>;
|
|
phy_type = "utmi";
|
|
};
|
|
|
|
usb1: usb@fe211000 {
|
|
compatible = "fsl-usb2-dr";
|
|
reg = <0x211000 0x1000>;
|
|
phy_type = "utmi";
|
|
};
|
|
|
|
sata: sata@220000 {
|
|
compatible = "fsl,pq-sata-v2";
|
|
reg = <0x220000 0x1000>;
|
|
interrupts = <68 0x2 0 0>;
|
|
sata-offset = <0x1000>;
|
|
sata-number = <2>;
|
|
sata-fpdma = <0>;
|
|
};
|
|
|
|
esdhc: esdhc@114000 {
|
|
compatible = "fsl,esdhc";
|
|
reg = <0x114000 0x1000>;
|
|
clock-frequency = <0>;
|
|
};
|
|
/include/ "qoriq-i2c-0.dtsi"
|
|
/include/ "qoriq-i2c-1.dtsi"
|
|
};
|
|
|
|
pcie@ffe200000 {
|
|
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@ffe201000 {
|
|
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@ffe202000 {
|
|
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
|
|
pcie@ffe203000 {
|
|
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
|
|
reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
|
|
law_trgt_if = <3>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
bus-range = <0x0 0xff>;
|
|
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
|
|
0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
|
|
};
|
|
};
|