mirror of
https://github.com/AsahiLinux/u-boot
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327 lines
10 KiB
C
327 lines
10 KiB
C
/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC824X 1
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#define CONFIG_MPC8240 1
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#define CONFIG_OXC 1
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_IDENT_STRING " [oxc] "
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#define CONFIG_WATCHDOG 1
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#define CONFIG_SHOW_ACTIVITY 1
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 9600
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP 1 /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_LOAD_ADDR 0x00100000 /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
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/*-----------------------------------------------------------------------
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* Boot options
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*/
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#define CONFIG_SERVERIP 10.0.0.1
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#define CONFIG_GATEWAYIP 10.0.0.1
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_LOADADDR 0x10000
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#define CONFIG_BOOTFILE "/mnt/ide0/p2/usr/tftp/oxc.elf"
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#define CONFIG_BOOTCOMMAND "tftp 0x10000 ; bootelf 0x10000"
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#define CONFIG_BOOTDELAY 10
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#define CFG_OXC_GENERATE_IP 1 /* Generate IP automatically */
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#define CFG_OXC_IPMASK 0x0A000000 /* 10.0.0.x */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_NET_MULTI /* Multi ethernet cards support */
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#define CONFIG_EEPRO100 /* Ethernet Express PRO 100 */
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#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define PCI_ENET0_IOADDR 0x80000000
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#define PCI_ENET0_MEMADDR 0x80000000
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#define PCI_ENET1_IOADDR 0x81000000
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#define PCI_ENET1_MEMADDR 0x81000000
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/*-----------------------------------------------------------------------
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* FLASH
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*/
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#define CFG_FLASH_PRELIMBASE 0xFF800000
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#define CFG_FLASH_BASE (0-flash_info[0].size)
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 32 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/*-----------------------------------------------------------------------
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* RAM
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_MAX_RAM_SIZE 0x10000000
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#define CFG_RESET_ADDRESS 0xFFF00100
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN 0x00030000
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#if (CFG_MONITOR_BASE < CFG_FLASH_PRELIMBASE)
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# define CFG_RAMBOOT 1
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#else
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# undef CFG_RAMBOOT
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#endif
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#define CFG_INIT_RAM_ADDR 0x40000000
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_SIZE 128
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
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#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
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#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
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/*-----------------------------------------------------------------------
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* Memory mapping
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*/
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#define CFG_CPLD_BASE 0xff000000 /* CPLD registers */
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#define CFG_CPLD_WATCHDOG (CFG_CPLD_BASE) /* Watchdog */
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#define CFG_CPLD_RESET (CFG_CPLD_BASE + 0x040000) /* Minor resets */
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#define CFG_UART_BASE (CFG_CPLD_BASE + 0x700000) /* debug UART */
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/*-----------------------------------------------------------------------
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* NS16550 Configuration
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*/
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE -4
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#define CFG_NS16550_CLK 1843200
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#define CFG_NS16550_COM1 CFG_UART_BASE
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/*-----------------------------------------------------------------------
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* I2C Bus
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*/
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#define CONFIG_I2C 1 /* I2C support on ... */
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#define CONFIG_HARD_I2C 1 /* ... hardware one */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
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#define CFG_I2C_EXPANDER0_ADDR 0x20 /* PCF8574 expander 0 addrerr */
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#define CFG_I2C_EXPANDER1_ADDR 0x21 /* PCF8574 expander 1 addrerr */
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#define CFG_I2C_EXPANDER2_ADDR 0x26 /* PCF8574 expander 2 addrerr */
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/*-----------------------------------------------------------------------
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR 0xFFF30000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */
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#define CONFIG_ENV_OVERWRITE 1 /* Allow modifying the environment */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
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#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
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#define CFG_EUMB_ADDR 0xFC000000
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/* MCCR1 */
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#define CFG_ROMNAL 0 /* rom/flash next access time */
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#define CFG_ROMFAL 19 /* rom/flash access time */
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/* MCCR2 */
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#define CFG_ASRISE 15 /* ASRISE=15 clocks */
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#define CFG_ASFALL 3 /* ASFALL=3 clocks */
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#define CFG_REFINT 1000 /* REFINT=1000 clocks */
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/* MCCR3 */
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#define CFG_BSTOPRE 0x35c /* Burst To Precharge */
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#define CFG_REFREC 7 /* Refresh to activate interval */
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#define CFG_RDLAT 4 /* data latency from read command */
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/* MCCR4 */
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#define CFG_PRETOACT 2 /* Precharge to activate interval */
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#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
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#define CFG_ACTORW 2 /* Activate to R/W */
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#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
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#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
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#define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length 2=4, 3=8 */
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#define CFG_REGISTERD_TYPE_BUFFER 1
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/* memory bank settings*/
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/*
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* only bits 20-29 are actually used from these vales to set the
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* start/end address the upper two bits will be 0, and the lower 20
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* bits will be set to 0x00000 for a start address, or 0xfffff for an
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* end address
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*/
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#define CFG_BANK0_START 0x00000000
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#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
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#define CFG_BANK0_ENABLE 1
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#define CFG_BANK1_START 0x00000000
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#define CFG_BANK1_END 0x00000000
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#define CFG_BANK1_ENABLE 0
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#define CFG_BANK2_START 0x00000000
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#define CFG_BANK2_END 0x00000000
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#define CFG_BANK2_ENABLE 0
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#define CFG_BANK3_START 0x00000000
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#define CFG_BANK3_END 0x00000000
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#define CFG_BANK3_ENABLE 0
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#define CFG_BANK4_START 0x00000000
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#define CFG_BANK4_END 0x00000000
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#define CFG_BANK4_ENABLE 0
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#define CFG_BANK5_START 0x00000000
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#define CFG_BANK5_END 0x00000000
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#define CFG_BANK5_ENABLE 0
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#define CFG_BANK6_START 0x00000000
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#define CFG_BANK6_END 0x00000000
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#define CFG_BANK6_ENABLE 0
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#define CFG_BANK7_START 0x00000000
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#define CFG_BANK7_END 0x00000000
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#define CFG_BANK7_ENABLE 0
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/*
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* Memory bank enable bitmask, specifying which of the banks defined above
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are actually present. MSB is for bank #7, LSB is for bank #0.
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*/
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#define CFG_BANK_ENABLE 0x01
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#define CFG_ODCR 0xff /* configures line driver impedances, */
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/* see 8240 book for bit definitions */
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#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
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/* currently accessed page in memory */
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/* see 8240 book for details */
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/* SDRAM 0 - 256MB */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* stack in DCACHE @ 1GB (no backing mem) */
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#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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/* PCI memory */
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#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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/* Flash, config addrs, etc */
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#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
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#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L CFG_IBAT0L
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#define CFG_DBAT0U CFG_IBAT0U
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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#define CFG_DBAT2L CFG_IBAT2L
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#define CFG_DBAT2U CFG_IBAT2U
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#define CFG_DBAT3L CFG_IBAT3L
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#define CFG_DBAT3U CFG_IBAT3U
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
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#if defined(CONFIG_CMD_KGDB)
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# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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