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The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
108 lines
3.4 KiB
C
108 lines
3.4 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_ddr_sdram.h>
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#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
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#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
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#endif
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void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num)
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{
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unsigned int i;
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volatile ccsr_ddr_t *ddr;
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switch (ctrl_num) {
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case 0:
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ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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break;
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case 1:
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ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
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break;
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default:
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printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
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return;
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}
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (i == 0) {
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out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs0_config, regs->cs[i].config);
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out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
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} else if (i == 1) {
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out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs1_config, regs->cs[i].config);
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out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
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} else if (i == 2) {
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out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs2_config, regs->cs[i].config);
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out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
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} else if (i == 3) {
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out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
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out_be32(&ddr->cs3_config, regs->cs[i].config);
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out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
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}
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}
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out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
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out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
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out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
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out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
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out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
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out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
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out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
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out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
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out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
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out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
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out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
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out_be32(&ddr->init_addr, regs->ddr_init_addr);
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out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
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out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
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out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
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out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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/*
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* For 8572 DDR1 erratum - DDR controller may enter illegal state
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* when operatiing in 32-bit bus mode with 4-beat bursts,
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* This erratum does not affect DDR3 mode, only for DDR2 mode.
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*/
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#ifdef CONFIG_MPC8572
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if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
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&& in_be32(&ddr->sdram_cfg) & 0x80000) {
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/* set DEBUG_1[31] */
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u32 temp = in_be32(&ddr->debug_1);
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out_be32(&ddr->debug_1, temp | 1);
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}
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#endif
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/*
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* 200 painful micro-seconds must elapse between
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* the DDR clock setup and the DDR config enable.
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*/
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udelay(200);
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asm volatile("sync;isync");
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out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
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/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
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while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
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udelay(10000); /* throttle polling rate */
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}
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}
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