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85c91cb694
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
589 lines
15 KiB
C
589 lines
15 KiB
C
/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <syscon.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cru_rk3328.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <dt-bindings/clock/rk3328-cru.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct pll_div {
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u32 refdiv;
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u32 fbdiv;
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u32 postdiv1;
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u32 postdiv2;
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u32 frac;
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};
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#define RATE_TO_DIV(input_rate, output_rate) \
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((input_rate) / (output_rate) - 1);
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#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
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.refdiv = _refdiv,\
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.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
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.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
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static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
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static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
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static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
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static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
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static const struct pll_div *apll_cfgs[] = {
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[APLL_816_MHZ] = &apll_816_cfg,
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[APLL_600_MHZ] = &apll_600_cfg,
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};
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enum {
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/* PLL_CON0 */
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLL_CON1 */
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_INTEGER_MODE = 1,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* PLL_CON2 */
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PLL_FRACDIV_SHIFT = 0,
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PLL_FRACDIV_MASK = 0xffffff,
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/* MODE_CON */
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APLL_MODE_SHIFT = 0,
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NPLL_MODE_SHIFT = 1,
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DPLL_MODE_SHIFT = 4,
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CPLL_MODE_SHIFT = 8,
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GPLL_MODE_SHIFT = 12,
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PLL_MODE_SLOW = 0,
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PLL_MODE_NORM,
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/* CLKSEL_CON0 */
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CLK_CORE_PLL_SEL_APLL = 0,
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CLK_CORE_PLL_SEL_GPLL,
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CLK_CORE_PLL_SEL_DPLL,
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CLK_CORE_PLL_SEL_NPLL,
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CLK_CORE_PLL_SEL_SHIFT = 6,
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CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
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CLK_CORE_DIV_SHIFT = 0,
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CLK_CORE_DIV_MASK = 0x1f,
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/* CLKSEL_CON1 */
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ACLKM_CORE_DIV_SHIFT = 4,
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ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
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PCLK_DBG_DIV_SHIFT = 0,
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PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
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/* CLKSEL_CON28 */
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ACLK_PERIHP_PLL_SEL_CPLL = 0,
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ACLK_PERIHP_PLL_SEL_GPLL,
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ACLK_PERIHP_PLL_SEL_HDMIPHY,
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ACLK_PERIHP_PLL_SEL_SHIFT = 6,
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ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
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ACLK_PERIHP_DIV_CON_SHIFT = 0,
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ACLK_PERIHP_DIV_CON_MASK = 0x1f,
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/* CLKSEL_CON29 */
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PCLK_PERIHP_DIV_CON_SHIFT = 4,
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PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
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HCLK_PERIHP_DIV_CON_SHIFT = 0,
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HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
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/* CLKSEL_CON22 */
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CLK_TSADC_DIV_CON_SHIFT = 0,
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CLK_TSADC_DIV_CON_MASK = 0x3ff,
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/* CLKSEL_CON23 */
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CLK_SARADC_DIV_CON_SHIFT = 0,
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CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT,
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/* CLKSEL_CON24 */
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CLK_PWM_PLL_SEL_CPLL = 0,
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CLK_PWM_PLL_SEL_GPLL,
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CLK_PWM_PLL_SEL_SHIFT = 15,
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CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
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CLK_PWM_DIV_CON_SHIFT = 8,
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CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
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CLK_SPI_PLL_SEL_CPLL = 0,
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CLK_SPI_PLL_SEL_GPLL,
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CLK_SPI_PLL_SEL_SHIFT = 7,
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CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
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CLK_SPI_DIV_CON_SHIFT = 0,
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CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
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/* CLKSEL_CON30 */
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CLK_SDMMC_PLL_SEL_CPLL = 0,
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CLK_SDMMC_PLL_SEL_GPLL,
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CLK_SDMMC_PLL_SEL_24M,
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CLK_SDMMC_PLL_SEL_USBPHY,
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CLK_SDMMC_PLL_SHIFT = 8,
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CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
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CLK_SDMMC_DIV_CON_SHIFT = 0,
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CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
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/* CLKSEL_CON32 */
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CLK_EMMC_PLL_SEL_CPLL = 0,
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CLK_EMMC_PLL_SEL_GPLL,
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CLK_EMMC_PLL_SEL_24M,
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CLK_EMMC_PLL_SEL_USBPHY,
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CLK_EMMC_PLL_SHIFT = 8,
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CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
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CLK_EMMC_DIV_CON_SHIFT = 0,
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CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
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/* CLKSEL_CON34 */
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CLK_I2C_PLL_SEL_CPLL = 0,
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CLK_I2C_PLL_SEL_GPLL,
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CLK_I2C_DIV_CON_MASK = 0x7f,
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CLK_I2C_PLL_SEL_MASK = 1,
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CLK_I2C1_PLL_SEL_SHIFT = 15,
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CLK_I2C1_DIV_CON_SHIFT = 8,
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CLK_I2C0_PLL_SEL_SHIFT = 7,
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CLK_I2C0_DIV_CON_SHIFT = 0,
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/* CLKSEL_CON35 */
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CLK_I2C3_PLL_SEL_SHIFT = 15,
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CLK_I2C3_DIV_CON_SHIFT = 8,
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CLK_I2C2_PLL_SEL_SHIFT = 7,
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CLK_I2C2_DIV_CON_SHIFT = 0,
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};
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#define VCO_MAX_KHZ (3200 * (MHz / KHz))
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#define VCO_MIN_KHZ (800 * (MHz / KHz))
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#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
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#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
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/*
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* the div restructions of pll in integer mode, these are defined in
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* * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
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*/
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#define PLL_DIV_MIN 16
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#define PLL_DIV_MAX 3200
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/*
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* How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
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* Formulas also embedded within the Fractional PLL Verilog model:
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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* Where:
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* FOUTVCO = Fractional PLL non-divided output frequency
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* FOUTPOSTDIV = Fractional PLL divided output frequency
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* (output of second post divider)
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* FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
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* REFDIV = Fractional PLL input reference clock divider
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* FBDIV = Integer value programmed into feedback divide
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*
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*/
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static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
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const struct pll_div *div)
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{
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u32 *pll_con;
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u32 mode_shift, mode_mask;
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pll_con = NULL;
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mode_shift = 0;
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switch (clk_id) {
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case CLK_ARM:
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pll_con = cru->apll_con;
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mode_shift = APLL_MODE_SHIFT;
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break;
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case CLK_DDR:
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pll_con = cru->dpll_con;
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mode_shift = DPLL_MODE_SHIFT;
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break;
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case CLK_CODEC:
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pll_con = cru->cpll_con;
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mode_shift = CPLL_MODE_SHIFT;
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break;
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case CLK_GENERAL:
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pll_con = cru->gpll_con;
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mode_shift = GPLL_MODE_SHIFT;
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break;
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case CLK_NEW:
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pll_con = cru->npll_con;
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mode_shift = NPLL_MODE_SHIFT;
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break;
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default:
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break;
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}
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mode_mask = 1 << mode_shift;
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/* All 8 PLLs have same VCO and output frequency range restrictions. */
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u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
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u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
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debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
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postdiv2=%d, vco=%u khz, output=%u khz\n",
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pll_con, div->fbdiv, div->refdiv, div->postdiv1,
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div->postdiv2, vco_khz, output_khz);
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assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
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output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
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div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
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/*
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* When power on or changing PLL setting,
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* we must force PLL into slow mode to ensure output stable clock.
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*/
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rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
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/* use integer mode */
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rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
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PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
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rk_clrsetreg(&pll_con[0],
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PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
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(div->fbdiv << PLL_FBDIV_SHIFT) |
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(div->postdiv1 << PLL_POSTDIV1_SHIFT));
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rk_clrsetreg(&pll_con[1],
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PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
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(div->postdiv2 << PLL_POSTDIV2_SHIFT) |
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(div->refdiv << PLL_REFDIV_SHIFT));
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/* waiting for pll lock */
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while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
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udelay(1);
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/* pll enter normal mode */
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rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
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}
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static void rkclk_init(struct rk3328_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/* configure gpll cpll */
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rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
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/* configure perihp aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
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hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
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pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
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rk_clrsetreg(&cru->clksel_con[28],
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ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
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ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
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rk_clrsetreg(&cru->clksel_con[29],
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PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
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pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
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hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
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}
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void rk3328_configure_cpu(struct rk3328_cru *cru,
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enum apll_frequencies apll_freq)
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{
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u32 clk_core_div;
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u32 aclkm_div;
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u32 pclk_dbg_div;
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rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
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clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
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aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
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pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
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rk_clrsetreg(&cru->clksel_con[0],
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CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
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CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
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clk_core_div << CLK_CORE_DIV_SHIFT);
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rk_clrsetreg(&cru->clksel_con[1],
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PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
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pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
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aclkm_div << ACLKM_CORE_DIV_SHIFT);
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}
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static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
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{
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u32 div, con;
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switch (clk_id) {
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case SCLK_I2C0:
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con = readl(&cru->clksel_con[34]);
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div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
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break;
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case SCLK_I2C1:
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con = readl(&cru->clksel_con[34]);
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div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
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break;
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case SCLK_I2C2:
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con = readl(&cru->clksel_con[35]);
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div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
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break;
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case SCLK_I2C3:
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con = readl(&cru->clksel_con[35]);
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div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
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break;
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default:
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printf("do not support this i2c bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(GPLL_HZ, div);
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}
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static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
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{
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int src_clk_div;
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src_clk_div = GPLL_HZ / hz;
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assert(src_clk_div - 1 < 127);
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switch (clk_id) {
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case SCLK_I2C0:
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rk_clrsetreg(&cru->clksel_con[34],
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CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
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(src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
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break;
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case SCLK_I2C1:
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rk_clrsetreg(&cru->clksel_con[34],
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CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
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(src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
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break;
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case SCLK_I2C2:
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rk_clrsetreg(&cru->clksel_con[35],
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CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
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(src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
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break;
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case SCLK_I2C3:
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rk_clrsetreg(&cru->clksel_con[35],
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CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
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(src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
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CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
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break;
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default:
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printf("do not support this i2c bus\n");
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return -EINVAL;
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}
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return DIV_TO_RATE(GPLL_HZ, src_clk_div);
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}
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static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
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{
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u32 div, con, con_id;
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switch (clk_id) {
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case HCLK_SDMMC:
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case SCLK_SDMMC:
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con_id = 30;
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break;
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case HCLK_EMMC:
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case SCLK_EMMC:
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con_id = 32;
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break;
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default:
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return -EINVAL;
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}
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con = readl(&cru->clksel_con[con_id]);
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div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
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if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
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== CLK_EMMC_PLL_SEL_24M)
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return DIV_TO_RATE(OSC_HZ, div);
|
|
else
|
|
return DIV_TO_RATE(GPLL_HZ, div);
|
|
}
|
|
|
|
static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
|
|
ulong clk_id, ulong set_rate)
|
|
{
|
|
int src_clk_div;
|
|
u32 con_id;
|
|
|
|
switch (clk_id) {
|
|
case HCLK_SDMMC:
|
|
case SCLK_SDMMC:
|
|
con_id = 30;
|
|
break;
|
|
case HCLK_EMMC:
|
|
case SCLK_EMMC:
|
|
con_id = 32;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
/* Select clk_sdmmc/emmc source from GPLL by default */
|
|
src_clk_div = GPLL_HZ / set_rate;
|
|
|
|
if (src_clk_div > 127) {
|
|
/* use 24MHz source for 400KHz clock */
|
|
src_clk_div = OSC_HZ / set_rate;
|
|
rk_clrsetreg(&cru->clksel_con[con_id],
|
|
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
|
|
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
|
|
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
|
|
} else {
|
|
rk_clrsetreg(&cru->clksel_con[con_id],
|
|
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
|
|
CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
|
|
(src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
|
|
}
|
|
|
|
return rk3328_mmc_get_clk(cru, clk_id);
|
|
}
|
|
|
|
static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
|
|
{
|
|
u32 div, con;
|
|
|
|
con = readl(&cru->clksel_con[24]);
|
|
div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
|
|
|
|
return DIV_TO_RATE(GPLL_HZ, div);
|
|
}
|
|
|
|
static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
|
|
{
|
|
u32 div = GPLL_HZ / hz;
|
|
|
|
rk_clrsetreg(&cru->clksel_con[24],
|
|
CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
|
|
CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
|
|
(div - 1) << CLK_PWM_DIV_CON_SHIFT);
|
|
|
|
return DIV_TO_RATE(GPLL_HZ, div);
|
|
}
|
|
|
|
static ulong rk3328_clk_get_rate(struct clk *clk)
|
|
{
|
|
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong rate = 0;
|
|
|
|
switch (clk->id) {
|
|
case 0 ... 29:
|
|
return 0;
|
|
case HCLK_SDMMC:
|
|
case HCLK_EMMC:
|
|
case SCLK_SDMMC:
|
|
case SCLK_EMMC:
|
|
rate = rk3328_mmc_get_clk(priv->cru, clk->id);
|
|
break;
|
|
case SCLK_I2C0:
|
|
case SCLK_I2C1:
|
|
case SCLK_I2C2:
|
|
case SCLK_I2C3:
|
|
rate = rk3328_i2c_get_clk(priv->cru, clk->id);
|
|
break;
|
|
case SCLK_PWM:
|
|
rate = rk3328_pwm_get_clk(priv->cru);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return rate;
|
|
}
|
|
|
|
static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
|
|
{
|
|
struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
|
|
ulong ret = 0;
|
|
|
|
switch (clk->id) {
|
|
case 0 ... 29:
|
|
return 0;
|
|
case HCLK_SDMMC:
|
|
case HCLK_EMMC:
|
|
case SCLK_SDMMC:
|
|
case SCLK_EMMC:
|
|
ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
|
|
break;
|
|
case SCLK_I2C0:
|
|
case SCLK_I2C1:
|
|
case SCLK_I2C2:
|
|
case SCLK_I2C3:
|
|
ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
|
|
break;
|
|
case SCLK_PWM:
|
|
ret = rk3328_pwm_set_clk(priv->cru, rate);
|
|
break;
|
|
default:
|
|
return -ENOENT;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct clk_ops rk3328_clk_ops = {
|
|
.get_rate = rk3328_clk_get_rate,
|
|
.set_rate = rk3328_clk_set_rate,
|
|
};
|
|
|
|
static int rk3328_clk_probe(struct udevice *dev)
|
|
{
|
|
struct rk3328_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
rkclk_init(priv->cru);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3328_clk_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct rk3328_clk_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->cru = (struct rk3328_cru *)dev_get_addr(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rk3328_clk_bind(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
|
|
/* The reset driver does not have a device node, so bind it here */
|
|
ret = device_bind_driver(gd->dm_root, "rk3328_sysreset", "reset", &dev);
|
|
if (ret)
|
|
printf("Warning: No RK3328 reset driver: ret=%d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct udevice_id rk3328_clk_ids[] = {
|
|
{ .compatible = "rockchip,rk3328-cru" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_rk3328_cru) = {
|
|
.name = "rockchip_rk3328_cru",
|
|
.id = UCLASS_CLK,
|
|
.of_match = rk3328_clk_ids,
|
|
.priv_auto_alloc_size = sizeof(struct rk3328_clk_priv),
|
|
.ofdata_to_platdata = rk3328_clk_ofdata_to_platdata,
|
|
.ops = &rk3328_clk_ops,
|
|
.bind = rk3328_clk_bind,
|
|
.probe = rk3328_clk_probe,
|
|
};
|