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https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
99 lines
2 KiB
C
99 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2004 Texas Instruments.
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* Copyright (C) 2009 David Brownell
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <init.h>
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#include <asm/arch/hardware.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* offsets from PLL controller base */
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#define PLLC_PLLCTL 0x100
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#define PLLC_PLLM 0x110
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#define PLLC_PREDIV 0x114
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#define PLLC_PLLDIV1 0x118
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#define PLLC_PLLDIV2 0x11c
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#define PLLC_PLLDIV3 0x120
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#define PLLC_POSTDIV 0x128
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#define PLLC_BPDIV 0x12c
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#define PLLC_PLLDIV4 0x160
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#define PLLC_PLLDIV5 0x164
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#define PLLC_PLLDIV6 0x168
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#define PLLC_PLLDIV7 0x16c
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#define PLLC_PLLDIV8 0x170
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#define PLLC_PLLDIV9 0x174
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unsigned int sysdiv[9] = {
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PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
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PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
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};
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int clk_get(enum davinci_clk_ids id)
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{
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int pre_div;
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int pllm;
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int post_div;
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int pll_out;
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unsigned int pll_base;
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pll_out = CFG_SYS_OSCIN_FREQ;
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if (id == DAVINCI_AUXCLK_CLKID)
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goto out;
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if ((id >> 16) == 1)
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pll_base = (unsigned int)davinci_pllc1_regs;
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else
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pll_base = (unsigned int)davinci_pllc0_regs;
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id &= 0xFFFF;
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/*
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* Lets keep this simple. Combining operations can result in
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* unexpected approximations
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*/
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pre_div = (readl(pll_base + PLLC_PREDIV) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pllm = readl(pll_base + PLLC_PLLM) + 1;
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pll_out /= pre_div;
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pll_out *= pllm;
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if (id == DAVINCI_PLLM_CLKID)
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goto out;
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post_div = (readl(pll_base + PLLC_POSTDIV) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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pll_out /= post_div;
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if (id == DAVINCI_PLLC_CLKID)
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goto out;
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pll_out /= (readl(pll_base + sysdiv[id - 1]) &
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DAVINCI_PLLC_DIV_MASK) + 1;
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out:
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return pll_out;
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}
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int set_cpu_clk_info(void)
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{
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gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000;
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/* DDR PHY uses an x2 input clock */
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gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 :
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(clk_get(DAVINCI_DDR_CLKID) / 1000000);
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gd->bd->bi_dsp_freq = 0;
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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return clk_get(DAVINCI_ARM_CLKID);
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}
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