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Patch by Haavard Skinnemoen, 6 Sep 2006 16:23:02 +0200 This patch adds common infrastructure code for the Atmel AVR32 architecture. See doc/README.AVR32 for details. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
148 lines
3.5 KiB
C
148 lines
3.5 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_PTRACE_H
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#define __ASM_AVR32_PTRACE_H
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/*
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* Status Register bits
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*/
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#define SR_H 0x40000000
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#define SR_R 0x20000000
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#define SR_J 0x10000000
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#define SR_DM 0x08000000
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#define SR_D 0x04000000
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#define MODE_NMI 0x01c00000
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#define MODE_EXCEPTION 0x01800000
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#define MODE_INT3 0x01400000
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#define MODE_INT2 0x01000000
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#define MODE_INT1 0x00c00000
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#define MODE_INT0 0x00800000
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#define MODE_SUPERVISOR 0x00400000
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#define MODE_USER 0x00000000
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#define MODE_MASK 0x01c00000
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#define SR_EM 0x00200000
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#define SR_I3M 0x00100000
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#define SR_I2M 0x00080000
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#define SR_I1M 0x00040000
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#define SR_I0M 0x00020000
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#define SR_GM 0x00010000
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#define MODE_SHIFT 22
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#define SR_EM_BIT 21
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#define SR_I3M_BIT 20
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#define SR_I2M_BIT 19
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#define SR_I1M_BIT 18
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#define SR_I0M_BIT 17
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#define SR_GM_BIT 16
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/* The user-visible part */
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#define SR_Q 0x00000010
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#define SR_V 0x00000008
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#define SR_N 0x00000004
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#define SR_Z 0x00000002
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#define SR_C 0x00000001
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/*
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* The order is defined by the stdsp instruction. r0 is stored first, so it
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* gets the highest address.
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*
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* Registers 0-12 are general-purpose registers (r12 is normally used for
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* the function return value).
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* Register 13 is the stack pointer
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* Register 14 is the link register
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* Register 15 is the program counter
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*/
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#define FRAME_SIZE_FULL 72
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#define REG_R12_ORIG 68
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#define REG_R0 64
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#define REG_R1 60
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#define REG_R2 56
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#define REG_R3 52
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#define REG_R4 48
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#define REG_R5 44
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#define REG_R6 40
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#define REG_R7 36
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#define REG_R8 32
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#define REG_R9 28
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#define REG_R10 34
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#define REG_R11 20
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#define REG_R12 16
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#define REG_SP 12
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#define REG_LR 8
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#define FRAME_SIZE_MIN 8
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#define REG_PC 4
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#define REG_SR 0
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#ifndef __ASSEMBLY__
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struct pt_regs {
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/* These are always saved */
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unsigned long sr;
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unsigned long pc;
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/* These are sometimes saved */
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unsigned long lr;
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unsigned long sp;
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unsigned long r12;
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unsigned long r11;
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unsigned long r10;
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unsigned long r9;
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unsigned long r8;
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unsigned long r7;
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unsigned long r6;
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unsigned long r5;
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unsigned long r4;
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unsigned long r3;
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unsigned long r2;
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unsigned long r1;
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unsigned long r0;
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/* Only saved on system call */
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unsigned long r12_orig;
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};
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#ifdef __KERNEL__
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# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
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# define instruction_pointer(regs) ((regs)->pc)
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extern void show_regs (struct pt_regs *);
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static __inline__ int valid_user_regs(struct pt_regs *regs)
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{
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/*
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* Some of the Java bits might be acceptable if/when we
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* implement some support for that stuff...
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*/
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if ((regs->sr & 0xffff0000) == 0)
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return 1;
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/*
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* Force status register flags to be sane and report this
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* illegal behaviour...
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*/
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regs->sr &= 0x0000ffff;
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return 0;
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}
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#endif
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#endif /* ! __ASSEMBLY__ */
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#endif /* __ASM_AVR32_PTRACE_H */
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