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https://github.com/AsahiLinux/u-boot
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4d86dd022e
This adds basic board support for TT-01 based on the Bluetechnix i.MX31 SOM. Currently only NOR-Flash boot is implemented. Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
254 lines
8.6 KiB
C
254 lines
8.6 KiB
C
/*
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* (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
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* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* Configuration settings for the HALE TT-01 board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/imx-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_ARM1136
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#define CONFIG_MX31
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#define CONFIG_MX31_HCLK_FREQ 26000000
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#define CONFIG_MX31_CLK32 32768
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
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#define CONFIG_SYS_TEXT_BASE 0xA0000000
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/*
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* Physical Memory Map:
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* CS settings are defined by i.MX31:
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* - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
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* - CS0 and CS1 are 128MB each, at A0000000 and A8000000
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* - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
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*
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* HALE set-up of the bluetechnix board for now is:
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* - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
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* - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
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* - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
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* the flash chip is a mirrorbit S29WS256N !
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* - the PSRAM is hooked to CS5 (0xB6000000)
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* - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
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* - 64Mbit = 8MByte (will go away in the production set-up)
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* - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
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* 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
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* - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
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*
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* u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
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* is not used right now. We should be able to reduce the SOM to NAND flash
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* only and boot from there.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE
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#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
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/* default load address, 1MB up the road */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
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/* The stack sizes are set up in start.S using the settings below */
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#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
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/* Size of malloc() pool, make sure possible frame buffer fits */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
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/* memtest works on all but the last 1MB (u-boot) and malloc area */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
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#define CONFIG_SYS_MEMTEST_END \
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(PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
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/* CFI FLASH driver setup */
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
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#define CONFIG_FLASH_SPANSION_S29WS_N
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/*
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* TODO: Bluetechnix (the supplier of the SOM) did define these values
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* in their original version of u-boot (1.2 or so). This should be
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* reviewed.
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*
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* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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* #define CONFIG_SYS_FLASH_PROTECTION
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*/
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#define CONFIG_SYS_FLASH_BASE CS0_BASE
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
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/*
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* FLASH and environment organization, only the Spansion chip is supported:
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* - it has 254 * 128kB + 8 * 32kB blocks
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* - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
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* and 2 sectors with 128k as environment =
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* A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
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* - this could be less, but this is only for developer versions of the board
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* and no-one is going to use the NOR flash anyway.
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*
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* Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
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* way to large, but it avoids ENV overwrite (when updating u-boot) in case
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* size breaks the next boundary (as it has with 128k).
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024) /* smaller for faster access */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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/* Hardware drivers */
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/*
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* on TT-01 UART1 pins are used by Audio, so we use UART2
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* TT-01 implements a hardware that turns off components depending on
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* the power level. In PL=1 the RS232 transceiver is usually off,
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* make sure that the transceiver is enabled during PL=1 for testing!
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_SYS_MX31_UART2
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#define CONFIG_MXC_SPI
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#define CONFIG_MXC_GPIO
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/* MC13783 connected to CSPI3 and SS0 */
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#define CONFIG_PMIC
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#define CONFIG_PMIC_SPI
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#define CONFIG_PMIC_FSL
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#define CONFIG_FSL_PMIC_BUS 2
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#define CONFIG_FSL_PMIC_CS 0
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#define CONFIG_FSL_PMIC_CLK 1000000
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#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
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#define CONFIG_FSL_PMIC_BITLEN 32
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#define CONFIG_RTC_MC13XXX
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* console is UART2 on TT-01 */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
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/* ethernet setup for the onboard smc9118 */
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#define CONFIG_MII
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#define CONFIG_SMC911X
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/* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
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#define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
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#define CONFIG_SMC911X_16_BIT
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/*
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* Command definition
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_NAND
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/*
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* #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
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* the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
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* a software locking scheme.
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*/
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#define CONFIG_BOOTDELAY 3
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/*
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* currently a default setting for booting via script is implemented
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* set user to login name and serverip to tftp host, define your
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* boot behaviour in bootscript.loginname
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootcmd=dhcp bootscript.$(user); source\0"
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#define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
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#define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
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/* Miscellaneous configurable options */
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#define CONFIG_HUSH_PARSER
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#define CONFIG_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "TT01> "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT)+16)
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/* max number of command args */
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_NAND_MXC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_MAX_CHIPS 1
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/*
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* actually this is nothing someone wants to configure!
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* CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
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* is not used by the driver.
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*/
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#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_MXC_NAND_HWECC
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/* the current u-boot driver does not use the nand flash setup! */
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#define CONFIG_SYS_NAND_LARGEPAGE
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/*
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* it's not 16 bit:
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* #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
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* the current u-boot mxc_nand.c tries to auto-detect, but this only
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* reads the boot settings during reset (which might be wrong)
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*/
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#endif /* __CONFIG_H */
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