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https://github.com/AsahiLinux/u-boot
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0dde7f5379
Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behaviour() function allows drivers to make these changes after the MMU is set up. It is implemented only for ARMv7 at present. This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
115 lines
3.4 KiB
C
115 lines
3.4 KiB
C
#ifndef __ASM_ARM_SYSTEM_H
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#define __ASM_ARM_SYSTEM_H
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#ifdef __KERNEL__
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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#define CPU_ARCH_ARMv4 2
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#define CPU_ARCH_ARMv4T 3
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#define CPU_ARCH_ARMv5 4
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#define CPU_ARCH_ARMv5T 5
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#define CPU_ARCH_ARMv5TE 6
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#define CPU_ARCH_ARMv5TEJ 7
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#define CPU_ARCH_ARMv6 8
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#define CPU_ARCH_ARMv7 9
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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* the compiler from one version to another so a bit of paranoia won't hurt.
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* This string is meant to be concatenated with the inline asm string and
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* will cause compilation to stop on mismatch.
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* (for details, see gcc PR 15089)
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#ifndef __ASSEMBLY__
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#define isb() __asm__ __volatile__ ("" : : : "memory")
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
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: : "r" (val) : "cc");
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isb();
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}
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = 0x12,
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DCACHE_WRITETHROUGH = 0x1a,
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DCACHE_WRITEBACK = 0x1e,
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};
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/* Size of an MMU section */
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enum {
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MMU_SECTION_SHIFT = 20,
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MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
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};
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/**
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* Change the cache settings for a region.
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*
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* \param start start address of memory region to change
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* \param size size of memory region to change
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* \param option dcache option to select
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*/
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void mmu_set_region_dcache_behaviour(u32 start, int size,
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enum dcache_option option);
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/**
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* Register an update to the page tables, and flush the TLB
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*
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* \param start start address of update in page table
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* \param stop stop address of update in page table
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*/
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void mmu_page_table_flush(unsigned long start, unsigned long stop);
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#endif /* __ASSEMBLY__ */
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#define arch_align_stack(x) (x)
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#endif /* __KERNEL__ */
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#endif
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