Ye Li dc77d0f9fc imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock ... The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW according to DDR DIV updating or DDR CLK halt status change. So DDR PCC disable/enable will trigger the lock up/down flow. We need wait until unlock to ensure clock is ready. And before configuring the DDRCLK DIV, we need polling the DDRLOCKED until it is unlocked. Otherwise writing ti DIV bits will not set. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>		2022-02-05 13:38:39 +01:00
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cgc.h	imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock	2022-02-05 13:38:39 +01:00
clock.h	imx8ulp: clock: Support to enable/disable the ADC1 clock	2022-02-05 13:38:39 +01:00
ddr.h	arm: imx: basic i.MX8ULP support	2021-08-09 14:46:50 +02:00
gpio.h	arm: imx: basic i.MX8ULP support	2021-08-09 14:46:50 +02:00
imx-regs.h	imx8ulp: clock: Support to enable/disable the ADC1 clock	2022-02-05 13:38:39 +01:00
imx8ulp-pins.h	imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display	2022-02-05 13:38:38 +01:00
iomux.h	arm: imx8ulp: add iomuxc support	2021-08-09 14:46:51 +02:00
mu_hal.h	arm: imx8ulp: release and configure XRDC at early phase	2021-08-09 14:46:51 +02:00
pcc.h	imx8ulp: clock: Support to enable/disable the ADC1 clock	2022-02-05 13:38:39 +01:00
rdc.h	imx8ulp: unify rdc functions	2021-08-09 14:46:51 +02:00
s400_api.h	drivers: misc: s400_api: Update API for fuse read and write	2021-08-09 14:46:51 +02:00
sys_proto.h	imx8ulp: Workaround LPOSC_TRIM fuse load issue	2022-02-05 13:38:39 +01:00
upower.h	imx8ulp: add upower api support	2021-08-09 14:46:51 +02:00