Paul Gortmaker e2b363ff53 sbc8548: Fix up local bus init to be frequency aware ... The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits. This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2012-01-11 13:59:17 -06:00
..
ddr.c	sbc8548: enable support for hardware SPD errata workaround	2012-01-11 13:59:14 -06:00
law.c	sbc8548: Make enabling SPD RAM configuration work	2012-01-11 13:59:07 -06:00
Makefile	punt unused clean/distclean targets	2011-10-15 22:20:36 +02:00
sbc8548.c	sbc8548: Fix up local bus init to be frequency aware	2012-01-11 13:59:17 -06:00
tlb.c	sbc8548: Make enabling SPD RAM configuration work	2012-01-11 13:59:07 -06:00