mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
9ed303dfa9
This patch add base support for LX2162AQDS board. LX2162AQDS board supports LX2162A family SoCs. This patch add basic support of platform. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: hui.song <hui.song_1@nxp.com> Signed-off-by: Manish Tomar <manish.tomar@nxp.com> Signed-off-by: Vikas Singh <vikas.singh@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
26 lines
518 B
Text
26 lines
518 B
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
|
/*
|
|
* NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20
|
|
*
|
|
* Some assumptions are made:
|
|
* * Mezzanine card M8 is connected to IO SLOT1
|
|
* (xlaui4 for DPMAC 1)
|
|
*
|
|
* Copyright 2020 NXP
|
|
*
|
|
*/
|
|
|
|
#include "fsl-lx2160a-qds.dtsi"
|
|
|
|
&dpmac1 {
|
|
status = "okay";
|
|
phy-handle = <&cortina_phy1_0>;
|
|
phy-connection-type = "xlaui4";
|
|
};
|
|
|
|
&emdio1_slot1 {
|
|
cortina_phy1_0: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x0>;
|
|
};
|
|
};
|