mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
269 lines
6.9 KiB
C
269 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/io.h>
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#include <errno.h>
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#ifdef CONFIG_OF_BOARD_SETUP
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#ifdef CONFIG_ARM
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#include <asm/arch/clock.h>
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#endif
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#include "pcie_layerscape.h"
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#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
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/*
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* Return next available LUT index.
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*/
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static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
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{
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if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
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return pcie->next_lut_index++;
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else
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return -ENOSPC; /* LUT is full */
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}
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/* returns the next available streamid for pcie, -errno if failed */
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static int ls_pcie_next_streamid(void)
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{
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static int next_stream_id = FSL_PEX_STREAM_ID_START;
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if (next_stream_id > FSL_PEX_STREAM_ID_END)
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return -EINVAL;
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return next_stream_id++;
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}
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static void lut_writel(struct ls_pcie *pcie, unsigned int value,
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unsigned int offset)
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{
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if (pcie->big_endian)
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out_be32(pcie->lut + offset, value);
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else
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out_le32(pcie->lut + offset, value);
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}
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/*
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* Program a single LUT entry
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*/
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static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
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u32 streamid)
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{
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/* leave mask as all zeroes, want to match all bits */
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lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
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lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
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}
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/*
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* An msi-map is a property to be added to the pci controller
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* node. It is a table, where each entry consists of 4 fields
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* e.g.:
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*
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* msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
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* [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
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*/
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static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
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u32 devid, u32 streamid)
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{
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u32 *prop;
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u32 phandle;
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int nodeoffset;
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uint svr;
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char *compat = NULL;
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/* find pci controller node */
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nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
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pcie->dbi_res.start);
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if (nodeoffset < 0) {
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
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svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A)
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compat = "fsl,ls2088a-pcie";
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else
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compat = CONFIG_FSL_PCIE_COMPAT;
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if (compat)
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nodeoffset = fdt_node_offset_by_compat_reg(blob,
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compat, pcie->dbi_res.start);
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#endif
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if (nodeoffset < 0)
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return;
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}
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/* get phandle to MSI controller */
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prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
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if (prop == NULL) {
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debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
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__func__, pcie->idx);
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return;
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}
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phandle = fdt32_to_cpu(*prop);
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/* set one msi-map row */
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
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fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
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}
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/*
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* An iommu-map is a property to be added to the pci controller
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* node. It is a table, where each entry consists of 4 fields
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* e.g.:
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*
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* iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
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* [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
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*/
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static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
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u32 devid, u32 streamid)
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{
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u32 *prop;
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u32 iommu_map[4];
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int nodeoffset;
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int lenp;
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uint svr;
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char *compat = NULL;
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/* find pci controller node */
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nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
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pcie->dbi_res.start);
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if (nodeoffset < 0) {
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
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svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A)
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compat = "fsl,ls2088a-pcie";
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else
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compat = CONFIG_FSL_PCIE_COMPAT;
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if (compat)
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nodeoffset = fdt_node_offset_by_compat_reg(blob,
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compat, pcie->dbi_res.start);
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#endif
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if (nodeoffset < 0)
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return;
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}
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/* get phandle to iommu controller */
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prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
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if (prop == NULL) {
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debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
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__func__, pcie->idx);
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return;
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}
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/* set iommu-map row */
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iommu_map[0] = cpu_to_fdt32(devid);
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iommu_map[1] = *++prop;
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iommu_map[2] = cpu_to_fdt32(streamid);
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iommu_map[3] = cpu_to_fdt32(1);
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if (devid == 0) {
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fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
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iommu_map, 16);
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} else {
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fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
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}
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}
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static void fdt_fixup_pcie(void *blob)
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{
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struct udevice *dev, *bus;
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struct ls_pcie *pcie;
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int streamid;
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int index;
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pci_dev_t bdf;
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/* Scan all known buses */
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for (pci_find_first_device(&dev);
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dev;
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pci_find_next_device(&dev)) {
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for (bus = dev; device_is_on_pci_bus(bus);)
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bus = bus->parent;
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pcie = dev_get_priv(bus);
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streamid = ls_pcie_next_streamid();
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if (streamid < 0) {
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debug("ERROR: no stream ids free\n");
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continue;
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}
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index = ls_pcie_next_lut_index(pcie);
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if (index < 0) {
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debug("ERROR: no LUT indexes free\n");
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continue;
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}
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/* the DT fixup must be relative to the hose first_busno */
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bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
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/* map PCI b.d.f to streamID in LUT */
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ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
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streamid);
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/* update msi-map in device tree */
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fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
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streamid);
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/* update iommu-map in device tree */
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fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
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streamid);
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}
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}
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#endif
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static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
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{
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int off;
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uint svr;
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char *compat = NULL;
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off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
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pcie->dbi_res.start);
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if (off < 0) {
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#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
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svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
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if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
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svr == SVR_LS2048A || svr == SVR_LS2044A ||
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svr == SVR_LS2081A || svr == SVR_LS2041A)
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compat = "fsl,ls2088a-pcie";
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else
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compat = CONFIG_FSL_PCIE_COMPAT;
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if (compat)
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off = fdt_node_offset_by_compat_reg(blob,
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compat, pcie->dbi_res.start);
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#endif
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if (off < 0)
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return;
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}
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if (pcie->enabled)
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fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
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else
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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}
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/* Fixup Kernel DT for PCIe */
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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struct ls_pcie *pcie;
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list_for_each_entry(pcie, &ls_pcie_list, list)
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ft_pcie_ls_setup(blob, pcie);
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#if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
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fdt_fixup_pcie(blob);
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#endif
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}
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#else /* !CONFIG_OF_BOARD_SETUP */
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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}
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#endif
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