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The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
34 lines
804 B
C
34 lines
804 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (c) 2017 Microsemi Corporation.
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* Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#include <asm/smp.h>
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/* Architecture-specific global data */
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struct arch_global_data {
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long boot_hart; /* boot hart id */
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#ifdef CONFIG_SIFIVE_CLINT
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void __iomem *clint; /* clint base address */
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#endif
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#ifdef CONFIG_ANDES_PLIC
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void __iomem *plic; /* plic base address */
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#endif
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#ifdef CONFIG_SMP
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struct ipi_data ipi[CONFIG_NR_CPUS];
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#endif
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ulong available_harts;
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};
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#include <asm-generic/global_data.h>
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#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp")
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#endif /* __ASM_GBL_DATA_H */
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