mirror of
https://github.com/AsahiLinux/u-boot
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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
97 lines
2.2 KiB
C
97 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2008
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <spd_sdram.h>
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#include <linux/delay.h>
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Autodetect onboard DDR SDRAM on 85xx platforms
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*
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* NOTE: Some of the hardcoded values are hardware dependant,
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* so this should be extended for other future boards
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* using this routine!
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*/
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phys_size_t fixed_sdram(void)
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{
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struct ccsr_ddr __iomem *ddr =
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(struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
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/*
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* Disable memory controller.
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*/
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ddr->cs0_config = 0;
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ddr->sdram_cfg = 0;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
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asm ("sync;isync;msync");
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udelay(1000);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
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asm ("sync; isync; msync");
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udelay(1000);
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if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
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/*
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* OK, size detected -> all done
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*/
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return CONFIG_SYS_SDRAM_SIZE<<20;
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}
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return 0; /* nothing found ! */
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}
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#endif
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#if defined(CONFIG_SYS_DRAM_TEST)
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int testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf ("SDRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("SDRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf ("SDRAM test passed.\n");
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return 0;
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}
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#endif
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