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https://github.com/AsahiLinux/u-boot
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f38391793f
There is the requirement on the chassis's backplane that when the clocks have been enabled, they then should not disappear. Resetting the Zarlink clocking chips at unit reset violates this requirement because the backplane clocks are not supplied during the reset time. To avoid this side effect, both the Zarlink clocking chips are reset only at power up. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
302 lines
6.9 KiB
C
302 lines
6.9 KiB
C
/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* Copyright 2011,2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "../common/common.h"
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#include "kmp204x.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
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return 0;
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}
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/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
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* 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
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* For I2C only the low state is activly driven and high state is pulled-up
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* by a resistor. Therefore the deblock GPIOs are used
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* -> as an active output to drive a low state
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* -> as an open-drain input to have a pulled-up high state
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*/
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/* QRIO GPIOs used for deblocking */
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#define DEBLOCK_PORT1 GPIO_A
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#define DEBLOCK_SCL1 20
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#define DEBLOCK_SDA1 21
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/* By default deblock GPIOs are floating */
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static void i2c_deblock_gpio_cfg(void)
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{
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/* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
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qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
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qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
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qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
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qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
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}
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void set_sda(int state)
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{
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qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
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}
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void set_scl(int state)
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{
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qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
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}
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int get_sda(void)
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{
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return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
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}
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int get_scl(void)
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{
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return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
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}
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#define ZL30158_RST 8
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#define BFTIC4_RST 0
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#define RSTRQSR1_WDT_RR 0x00200000
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#define RSTRQSR1_SW_RR 0x00100000
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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bool cpuwd_flag = false;
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/* configure mode for uP reset request */
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qrio_uprstreq(UPREQ_CORE_RST);
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/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
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setbits_be32(&gur->ddrclkdr, 0x001f000f);
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/* set reset reason according CPU register */
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if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
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RSTRQSR1_WDT_RR)
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cpuwd_flag = true;
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qrio_cpuwd_flag(cpuwd_flag);
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/* clear CPU bits by writing 1 */
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setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
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/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
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qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
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/* and enable WD on it */
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qrio_wdmask(BFTIC4_RST, true);
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/* set the ZL30138's prstcfg to reset at power-up only */
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qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
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/* and take it out of reset as soon as possible (needed for Hooper) */
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qrio_prst(ZL30158_RST, false, false);
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return 0;
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}
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int board_early_init_r(void)
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{
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int ret = 0;
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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set_liodns();
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setup_portals();
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ret = trigger_fpga_config();
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if (ret)
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printf("error triggering PCIe FPGA config\n");
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/* enable the Unit LED (red) & Boot LED (on) */
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qrio_set_leds();
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/* enable Application Buffer */
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qrio_enable_app_buffer();
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return ret;
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}
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unsigned long get_board_sys_clk(unsigned long dummy)
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{
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return 66666666;
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}
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#define ETH_FRONT_PHY_RST 15
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#define QSFP2_RST 11
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#define QSFP1_RST 10
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#define ZL30343_RST 9
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int misc_init_f(void)
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{
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/* configure QRIO pis for i2c deblocking */
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i2c_deblock_gpio_cfg();
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/* configure the front phy's prstcfg and take it out of reset */
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qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prst(ETH_FRONT_PHY_RST, false, false);
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/* set the ZL30343 prstcfg to reset at power-up only */
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qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
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/* and enable the WD on it */
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qrio_wdmask(ZL30343_RST, true);
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/* set the QSFPs' prstcfg to reset at power-up and unit rst only */
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qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
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/* and enable the WD on them */
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qrio_wdmask(QSFP1_RST, true);
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qrio_wdmask(QSFP2_RST, true);
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return 0;
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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{
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serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
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SRDS_PLLCR0_RFCK_SEL_125};
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unsigned int i;
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/* check SERDES reference clocks */
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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u32 actual = in_be32(®s->bank[i].pllcr0);
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actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
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if (actual != expected[i]) {
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printf("Warning: SERDES bank %u expects reference \
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clock %sMHz, but actual is %sMHz\n", i + 1,
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serdes_clock_to_string(expected[i]),
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serdes_clock_to_string(actual));
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}
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}
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return 0;
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}
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#if defined(CONFIG_HUSH_INIT_VAR)
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int hush_init_var(void)
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{
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ivm_read_eeprom();
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return 0;
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}
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#endif
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#if defined(CONFIG_LAST_STAGE_INIT)
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int last_stage_init(void)
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{
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#if defined(CONFIG_KMCOGE4)
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/* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
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struct bfticu_iomap *bftic4 =
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(struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
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u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
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if (dip_switch != 0) {
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/* start bootloader */
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puts("DIP: Enabled\n");
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setenv("actual_bank", "0");
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}
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#endif
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set_km_env();
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return 0;
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}
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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void fdt_fixup_fman_mac_addresses(void *blob)
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{
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int node, i, ret;
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char *tmp, *end;
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unsigned char mac_addr[6];
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/* get the mac addr from env */
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tmp = getenv("ethaddr");
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if (!tmp) {
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printf("ethaddr env variable not defined\n");
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return;
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}
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for (i = 0; i < 6; i++) {
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mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
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if (tmp)
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tmp = (*end) ? end+1 : end;
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}
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/* find the correct fdt ethernet path and correct it */
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node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
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if (node < 0) {
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printf("no /soc/fman/ethernet path offset\n");
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return;
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}
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ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
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if (ret) {
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printf("error setting local-mac-address property\n");
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return;
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}
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}
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#endif
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
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fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_fman_mac_addresses(blob);
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#endif
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}
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#if defined(CONFIG_POST)
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/* DIC26_SELFTEST GPIO used to start factory test sw */
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#define SELFTEST_PORT GPIO_A
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#define SELFTEST_PIN 31
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int post_hotkeys_pressed(void)
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{
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qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
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return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
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}
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#endif
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