mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
33846df28f
The NAND flash on the TQM8548_BE modules requires a short delay after running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE requires a further short delay after writing out a buffer. Normally the R/B pin should be checked, but it's not connected on the TQM8548_BE. The corresponding Linux FSL UPM driver uses similar delay points at the same locations. To manage these extra delays in a more general way, I introduced the "wait_flags" field allowing the board-specific driver to specify various types of extra delay. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
48 lines
1 KiB
C
48 lines
1 KiB
C
/*
|
|
* FSL UPM NAND driver
|
|
*
|
|
* Copyright (C) 2007 MontaVista Software, Inc.
|
|
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef __LINUX_MTD_NAND_FSL_UPM
|
|
#define __LINUX_MTD_NAND_FSL_UPM
|
|
|
|
#include <linux/mtd/nand.h>
|
|
|
|
#define FSL_UPM_WAIT_RUN_PATTERN 0x1
|
|
#define FSL_UPM_WAIT_WRITE_BYTE 0x2
|
|
#define FSL_UPM_WAIT_WRITE_BUFFER 0x4
|
|
|
|
struct fsl_upm {
|
|
void __iomem *mdr;
|
|
void __iomem *mxmr;
|
|
void __iomem *mar;
|
|
void __iomem *io_addr;
|
|
};
|
|
|
|
struct fsl_upm_nand {
|
|
struct fsl_upm upm;
|
|
|
|
int width;
|
|
int upm_cmd_offset;
|
|
int upm_addr_offset;
|
|
int upm_mar_chip_offset;
|
|
int wait_flags;
|
|
int (*dev_ready)(int chip_nr);
|
|
int chip_delay;
|
|
int chip_offset;
|
|
int chip_nr;
|
|
|
|
/* no need to fill */
|
|
int last_ctrl;
|
|
};
|
|
|
|
extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun);
|
|
|
|
#endif
|