mirror of
https://github.com/AsahiLinux/u-boot
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93e1459641
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Drop changes for PEP 4 following python tools] Signed-off-by: Tom Rini <trini@ti.com>
322 lines
11 KiB
C
322 lines
11 KiB
C
/*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Configuation settings for the PDNB3 board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_IXP425 1 /* This is an IXP425 CPU */
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#define CONFIG_PDNB3 1 /* on an PDNB3 board */
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#define CONFIG_MACH_TYPE 1002
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#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */
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#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */
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/*
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* Ethernet
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*/
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#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */
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#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */
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#define CONFIG_HAS_ETH1
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#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
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/*
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* Misc configuration options
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*/
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#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */
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#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (1 << 20)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_IXP_SERIAL
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_PING
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#if !defined(CONFIG_SCPU)
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#define CONFIG_CMD_NAND
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */
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#define CONFIG_IXP425_TIMER_CLK 66666666
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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/***************************************************************
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* Platform/Board specific defines start here.
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***************************************************************/
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/*-----------------------------------------------------------------------
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* Default configuration (environment varibles...)
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*----------------------------------------------------------------------*/
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#undef CONFIG_BOOTARGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"hostname=pdnb3\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \
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"mtdparts=${mtdparts}\0" \
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"flash_nfs=run nfsargs addip addtty;" \
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"bootm ${kernel_addr}\0" \
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"flash_self=run ramargs addip addtty;" \
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"bootm ${kernel_addr} ${ramdisk_addr}\0" \
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"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
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"bootm\0" \
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"rootpath=/opt/buildroot\0" \
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"bootfile=/tftpboot/netbox/uImage\0" \
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"kernel_addr=50080000\0" \
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"ramdisk_addr=50200000\0" \
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"load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \
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"update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \
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"cp.b 100000 50000000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load update\0" \
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"ipaddr=10.0.0.233\0" \
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"serverip=10.0.0.152\0" \
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"netmask=255.255.0.0\0" \
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"ethaddr=c6:6f:13:36:f3:81\0" \
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"eth1addr=c6:6f:13:36:f3:82\0" \
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"mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \
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"4k@508k(renv)\0" \
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""
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#define CONFIG_BOOTCOMMAND "run net_nfs"
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define CONFIG_SYS_TEXT_BASE 0x50000000
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#define CONFIG_SYS_FLASH_BASE 0x50000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#if defined(CONFIG_SCPU)
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */
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#else
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#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */
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#endif
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/*
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* Expansion bus settings
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*/
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#if defined(CONFIG_SCPU)
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#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */
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#else
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#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */
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#endif
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#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */
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/*
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* SDRAM settings
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*/
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#define CONFIG_SYS_SDR_CONFIG 0x18
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#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
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#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
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/*
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* FLASH and environment organization
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*/
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#if defined(CONFIG_SCPU)
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#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
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#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
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#endif
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
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#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
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#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
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#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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/*
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* The following defines are added for buggy IOP480 byte interface.
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* All other boards should use the standard values (CPCI405 etc.)
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*/
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#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
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#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
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#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#if defined(CONFIG_SCPU)
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/* no redundant environment on SCPU */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
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#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#else
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#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */
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#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#endif
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#if !defined(CONFIG_SCPU)
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/*
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* NAND-FLASH stuff
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */
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#endif
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/*
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* GPIO settings
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*/
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/* FPGA program pin configuration */
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#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/
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#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */
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#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */
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#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */
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#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */
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/* other GPIO's */
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#define CONFIG_SYS_GPIO_RESTORE_INT 0
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#define CONFIG_SYS_GPIO_RESTART_INT 1
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#define CONFIG_SYS_GPIO_SYS_RUNNING 2
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#define CONFIG_SYS_GPIO_PCI_INTA 3
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#define CONFIG_SYS_GPIO_PCI_INTB 4
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#define CONFIG_SYS_GPIO_I2C_SCL 6
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#define CONFIG_SYS_GPIO_I2C_SDA 7
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#define CONFIG_SYS_GPIO_FPGA_RESET 9
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#define CONFIG_SYS_GPIO_CLK_33M 15
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/*
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* I2C stuff
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*/
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/* enable I2C and select the hardware/software driver */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL)
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#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA)
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#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL)
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#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA)
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#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA)
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#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0)
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#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \
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else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA)
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#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \
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else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL)
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#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
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/*
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* I2C RTC
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*/
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#if 0 /* test-only */
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#define CONFIG_RTC_DS1340 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#else
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/* M41T11 Serial Access Timekeeper(R) SRAM */
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#define CONFIG_RTC_M41T11 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
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#endif
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/*
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* Spartan3 FPGA configuration support
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*/
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#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */
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#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/
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#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */
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#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */
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#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */
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#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
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#endif /* __CONFIG_H */
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