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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
207 lines
6.6 KiB
C
207 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Sun8i platform dram controller register and constant defines
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*
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* (C) Copyright 2007-2015 Allwinner Technology Co.
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* Jerry Wang <wangflord@allwinnertech.com>
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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*/
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#ifndef _SUNXI_DRAM_SUN8I_A83T_H
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#define _SUNXI_DRAM_SUN8I_A83T_H
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struct sunxi_mctl_com_reg {
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u32 cr; /* 0x00 */
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u32 ccr; /* 0x04 controller configuration register */
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u32 dbgcr; /* 0x08 */
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u8 res0[0x4]; /* 0x0c */
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u32 mcr0_0; /* 0x10 */
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u32 mcr1_0; /* 0x14 */
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u32 mcr0_1; /* 0x18 */
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u32 mcr1_1; /* 0x1c */
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u32 mcr0_2; /* 0x20 */
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u32 mcr1_2; /* 0x24 */
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u32 mcr0_3; /* 0x28 */
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u32 mcr1_3; /* 0x2c */
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u32 mcr0_4; /* 0x30 */
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u32 mcr1_4; /* 0x34 */
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u32 mcr0_5; /* 0x38 */
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u32 mcr1_5; /* 0x3c */
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u32 mcr0_6; /* 0x40 */
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u32 mcr1_6; /* 0x44 */
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u32 mcr0_7; /* 0x48 */
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u32 mcr1_7; /* 0x4c */
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u32 mcr0_8; /* 0x50 */
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u32 mcr1_8; /* 0x54 */
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u32 mcr0_9; /* 0x58 */
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u32 mcr1_9; /* 0x5c */
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u32 mcr0_10; /* 0x60 */
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u32 mcr1_10; /* 0x64 */
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u32 mcr0_11; /* 0x68 */
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u32 mcr1_11; /* 0x6c */
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u32 mcr0_12; /* 0x70 */
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u32 mcr1_12; /* 0x74 */
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u32 mcr0_13; /* 0x78 */
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u32 mcr1_13; /* 0x7c */
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u32 mcr0_14; /* 0x80 */
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u32 mcr1_14; /* 0x84 */
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u32 mcr0_15; /* 0x88 */
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u32 mcr1_15; /* 0x8c */
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u32 bwcr; /* 0x90 */
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u32 maer; /* 0x94 */
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u32 mapr; /* 0x98 */
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u32 mcgcr; /* 0x9c */
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u32 bwctr; /* 0xa0 */
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u8 res2[0x8]; /* 0xa4 */
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u32 swoffr; /* 0xac */
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u8 res3[0x10]; /* 0xb0 */
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u32 swonr; /* 0xc0 */
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u8 res4[0x3c]; /* 0xc4 */
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u32 mdfscr; /* 0x100 */
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u32 mdfsmer; /* 0x104 */
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};
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struct sunxi_mctl_ctl_reg {
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u32 pir; /* 0x00 */
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u32 pwrctl; /* 0x04 */
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u32 mrctrl0; /* 0x08 */
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u32 clken; /* 0x0c */
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u32 pgsr0; /* 0x10 */
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u32 pgsr1; /* 0x14 */
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u32 statr; /* 0x18 */
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u8 res1[0x14]; /* 0x1c */
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u32 mr0; /* 0x30 */
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u32 mr1; /* 0x34 */
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u32 mr2; /* 0x38 */
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u32 mr3; /* 0x3c */
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u32 pllgcr; /* 0x40 */
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u32 ptr0; /* 0x44 */
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u32 ptr1; /* 0x48 */
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u32 ptr2; /* 0x4c */
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u32 ptr3; /* 0x50 */
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u32 ptr4; /* 0x54 */
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u32 dramtmg0; /* 0x58 dram timing parameters register 0 */
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u32 dramtmg1; /* 0x5c dram timing parameters register 1 */
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u32 dramtmg2; /* 0x60 dram timing parameters register 2 */
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u32 dramtmg3; /* 0x64 dram timing parameters register 3 */
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u32 dramtmg4; /* 0x68 dram timing parameters register 4 */
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u32 dramtmg5; /* 0x6c dram timing parameters register 5 */
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u32 dramtmg6; /* 0x70 dram timing parameters register 6 */
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u32 dramtmg7; /* 0x74 dram timing parameters register 7 */
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u32 dramtmg8; /* 0x78 dram timing parameters register 8 */
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u32 odtcfg; /* 0x7c */
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u32 pitmg0; /* 0x80 */
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u32 pitmg1; /* 0x84 */
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u8 res2[0x4]; /* 0x88 */
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u32 rfshctl0; /* 0x8c */
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u32 rfshtmg; /* 0x90 */
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u32 rfshctl1; /* 0x94 */
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u32 pwrtmg; /* 0x98 */
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u8 res3[0x20]; /* 0x9c */
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u32 dqsgmr; /* 0xbc */
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u32 dtcr; /* 0xc0 */
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u32 dtar0; /* 0xc4 */
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u32 dtar1; /* 0xc8 */
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u32 dtar2; /* 0xcc */
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u32 dtar3; /* 0xd0 */
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u32 dtdr0; /* 0xd4 */
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u32 dtdr1; /* 0xd8 */
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u32 dtmr0; /* 0xdc */
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u32 dtmr1; /* 0xe0 */
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u32 dtbmr; /* 0xe4 */
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u32 catr0; /* 0xe8 */
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u32 catr1; /* 0xec */
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u32 dtedr0; /* 0xf0 */
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u32 dtedr1; /* 0xf4 */
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u8 res4[0x8]; /* 0xf8 */
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u32 pgcr0; /* 0x100 */
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u32 pgcr1; /* 0x104 */
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u32 pgcr2; /* 0x108 */
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u32 pgcr3; /* 0x10c */
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u32 iovcr0; /* 0x110 */
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u32 iovcr1; /* 0x114 */
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u32 dqsdr; /* 0x118 */
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u32 dxccr; /* 0x11c */
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u32 odtmap; /* 0x120 */
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u32 zqctl0; /* 0x124 */
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u32 zqctl1; /* 0x128 */
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u8 res6[0x14]; /* 0x12c */
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u32 zqncr; /* 0x140 zq control register 0 */
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u32 zqnpr; /* 0x144 zq control register 1 */
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u32 zqndr; /* 0x148 zq control register 2 */
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u32 zqnsr; /* 0x14c zq status register 0 */
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u32 res7; /* 0x150 zq status register 1 */
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u8 res8[0x6c]; /* 0x154 */
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u32 sched; /* 0x1c0 */
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u32 perfhpr0; /* 0x1c4 */
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u32 perfhpr1; /* 0x1c8 */
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u32 perflpr0; /* 0x1cc */
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u32 perflpr1; /* 0x1d0 */
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u32 perfwr0; /* 0x1d4 */
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u32 perfwr1; /* 0x1d8 */
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};
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#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x)
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#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x)
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#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x)
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#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x)
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#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x)
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#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x)
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#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x)
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#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x)
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#define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x))
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#define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x)
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#define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300)
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#define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x)
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#define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x)
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#define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x)
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#define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x)
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#define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x)
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#define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x)
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#define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x)
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#define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880)
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#define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888)
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#define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800)
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#define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x)
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#define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x)
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/*
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* DRAM common (sunxi_mctl_com_reg) register constants.
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*/
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#define MCTL_CR_RANK_MASK (3 << 0)
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#define MCTL_CR_RANK(x) (((x) - 1) << 0)
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#define MCTL_CR_BANK_MASK (3 << 2)
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#define MCTL_CR_BANK(x) ((x) << 2)
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#define MCTL_CR_ROW_MASK (0xf << 4)
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#define MCTL_CR_ROW(x) (((x) - 1) << 4)
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#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
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#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
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#define MCTL_CR_BUSW_MASK (7 << 12)
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#define MCTL_CR_BUSW8 (0 << 12)
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#define MCTL_CR_BUSW16 (1 << 12)
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#define MCTL_CR_SEQUENCE (1 << 15)
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#define MCTL_CR_DRAM_TYPE(x) ((x) << 16)
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#define MCTL_CR_CHANNEL_MASK (1 << 19)
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#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
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#define MCTL_CR_UNKNOWN (0x4 << 20)
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#define MCTL_CR_CS1_CONTROL(x) ((x) << 24)
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/* DRAM control (sunxi_mctl_ctl_reg) register constants */
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#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */
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#define MCTL_MR1 0x40
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#define MCTL_MR2 0x18 /* CWL=8 */
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#define MCTL_MR3 0x0
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#define MCTL_LPDDR3_MR0 0x0
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#define MCTL_LPDDR3_MR1 0xc3 /* twr=8, bl=8 */
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#define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */
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#define MCTL_LPDDR3_MR3 0x0
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#define DRAM_TYPE_DDR3 3
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#define DRAM_TYPE_LPDDR3 7
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#endif /* _SUNXI_DRAM_SUN8I_A83T_H */
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