mirror of
https://github.com/AsahiLinux/u-boot
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3f2b4d7220
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
105 lines
2 KiB
C
105 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <init.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8ulp-pins.h>
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#include <dm/uclass.h>
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#include <dm/device.h>
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#include <dm/uclass-internal.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/rdc.h>
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#include <asm/arch/upower.h>
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DECLARE_GLOBAL_DATA_PTR;
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void spl_dram_init(void)
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{
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init_clk_ddr();
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ddr_init(&dram_timing);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_BOOTROM;
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}
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int power_init_board(void)
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{
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u32 pmic_reg;
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/* PMIC set bucks1-4 to PWM mode */
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upower_pmic_i2c_read(0x10, &pmic_reg);
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upower_pmic_i2c_read(0x14, &pmic_reg);
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upower_pmic_i2c_read(0x21, &pmic_reg);
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upower_pmic_i2c_read(0x2e, &pmic_reg);
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upower_pmic_i2c_write(0x10, 0x3d);
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upower_pmic_i2c_write(0x14, 0x7d);
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upower_pmic_i2c_write(0x21, 0x7d);
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upower_pmic_i2c_write(0x2e, 0x3d);
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upower_pmic_i2c_read(0x10, &pmic_reg);
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upower_pmic_i2c_read(0x14, &pmic_reg);
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upower_pmic_i2c_read(0x21, &pmic_reg);
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upower_pmic_i2c_read(0x2e, &pmic_reg);
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/* Set buck3 to 1.1v OD */
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upower_pmic_i2c_write(0x22, 0x28);
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return 0;
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}
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void spl_board_init(void)
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{
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struct udevice *dev;
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uclass_find_first_device(UCLASS_MISC, &dev);
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for (; dev; uclass_find_next_device(&dev)) {
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if (device_probe(dev))
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continue;
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}
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board_early_init_f();
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preloader_console_init();
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puts("Normal Boot\n");
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/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
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upower_init();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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/* This must place after upower init, so access to MDA and MRC are valid */
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/* Init XRDC MDA */
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xrdc_init_mda();
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/* Init XRDC MRC for VIDEO, DSP domains */
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xrdc_init_mrc();
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}
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void board_init_f(ulong dummy)
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{
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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timer_init();
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arch_cpu_init();
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board_init_r(NULL, 0);
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}
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