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https://github.com/AsahiLinux/u-boot
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7add47959e
Since commitde39dc7162("arm: armv7-a: Compile and tune for armv7-a instead of armv5") is used -march=armv7-a option for Omap3 platforms. With directive ".arch_extension sec" it is possible for -march=armv7-a to directly use ARM SMC instruction. So enable ".arch_extension sec" in Omap3 lowlevel_init.S and replace hand assembled ".word 0xe1600071" by "SMC #1". Since commit51d0638650("arm: omap-common: add secure smc entry") same pattern is already used in arch/arm/cpu/armv7/omap-common/lowlevel_init.S. Signed-off-by: Pali Rohár <pali@kernel.org>
480 lines
12 KiB
ArmAsm
480 lines
12 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Board specific setup info
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*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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*
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* Initial Code by:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*/
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#include <config.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/clocks_omap3.h>
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#include <linux/linkage.h>
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.arch_extension sec
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/*
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* Funtion for making PPA HAL API calls in secure devices
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* Input:
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* R0 - Service ID
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* R1 - paramer list
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*/
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ENTRY(do_omap3_emu_romcode_call)
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PUSH {r4-r12, lr} @ Save all registers from ROM code!
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MOV r12, r0 @ Copy the Secure Service ID in R12
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MOV r3, r1 @ Copy the pointer to va_list in R3
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MOV r1, #0 @ Process ID - 0
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MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
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@ to va_list in R3
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MOV r6, #0xFF @ Indicate new Task call
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c10, 5 @ DMB
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SMC #1 @ Call PPA service
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POP {r4-r12, pc}
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ENDPROC(do_omap3_emu_romcode_call)
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#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
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/**************************************************************************
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* cpy_clk_code: relocates clock code into SRAM where its safer to execute
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* R1 = SRAM destination address.
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*************************************************************************/
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ENTRY(cpy_clk_code)
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/* Copy DPLL code into SRAM */
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adr r0, go_to_speed /* copy from start of go_to_speed... */
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adr r2, go_to_speed_end /* ... up to start of go_to_speed_end */
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next2:
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ldmia r0!, {r3 - r10} /* copy from source address [r0] */
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stmia r1!, {r3 - r10} /* copy to target address [r1] */
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cmp r0, r2 /* until source end address [r2] */
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blo next2
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mov pc, lr /* back to caller */
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ENDPROC(cpy_clk_code)
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/* ***************************************************************************
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* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
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* -executed from SRAM.
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* R0 = CM_CLKEN_PLL-bypass value
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* R1 = CM_CLKSEL1_PLL-m, n, and divider values
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* R2 = CM_CLKSEL_CORE-divider values
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* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
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*
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* Note: If core unlocks/relocks and SDRAM is running fast already it gets
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* confused. A reset of the controller gets it back. Taking away its
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* L3 when its not in self refresh seems bad for it. Normally, this
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* code runs from flash before SDR is init so that should be ok.
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****************************************************************************/
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ENTRY(go_to_speed)
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stmfd sp!, {r4 - r6}
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/* move into fast relock bypass */
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ldr r4, pll_ctl_add
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str r0, [r4]
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wait1:
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ldr r5, [r3] /* get status */
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and r5, r5, #0x1 /* isolate core status */
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cmp r5, #0x1 /* still locked? */
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beq wait1 /* if lock, loop */
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/* set new dpll dividers _after_ in bypass */
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ldr r5, pll_div_add1
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str r1, [r5] /* set m, n, m2 */
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ldr r5, pll_div_add2
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str r2, [r5] /* set l3/l4/.. dividers*/
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ldr r5, pll_div_add3 /* wkup */
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ldr r2, pll_div_val3 /* rsm val */
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str r2, [r5]
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ldr r5, pll_div_add4 /* gfx */
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ldr r2, pll_div_val4
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str r2, [r5]
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ldr r5, pll_div_add5 /* emu */
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ldr r2, pll_div_val5
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str r2, [r5]
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/* now prepare GPMC (flash) for new dpll speed */
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/* flash needs to be stable when we jump back to it */
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ldr r5, flash_cfg3_addr
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ldr r2, flash_cfg3_val
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str r2, [r5]
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ldr r5, flash_cfg4_addr
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ldr r2, flash_cfg4_val
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str r2, [r5]
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ldr r5, flash_cfg5_addr
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ldr r2, flash_cfg5_val
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str r2, [r5]
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ldr r5, flash_cfg1_addr
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ldr r2, [r5]
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orr r2, r2, #0x3 /* up gpmc divider */
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str r2, [r5]
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/* lock DPLL3 and wait a bit */
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orr r0, r0, #0x7 /* set up for lock mode */
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str r0, [r4] /* lock */
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nop /* ARM slow at this point working at sys_clk */
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nop
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nop
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nop
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wait2:
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ldr r5, [r3] /* get status */
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and r5, r5, #0x1 /* isolate core status */
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cmp r5, #0x1 /* still locked? */
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bne wait2 /* if lock, loop */
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nop
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nop
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nop
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nop
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ldmfd sp!, {r4 - r6}
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mov pc, lr /* back to caller, locked */
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ENDPROC(go_to_speed)
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_go_to_speed: .word go_to_speed
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/* these constants need to be close for PIC code */
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/* The Nor has to be in the Flash Base CS0 for this condition to happen */
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flash_cfg1_addr:
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.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
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flash_cfg3_addr:
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.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
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flash_cfg3_val:
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.word STNOR_GPMC_CONFIG3
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flash_cfg4_addr:
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.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
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flash_cfg4_val:
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.word STNOR_GPMC_CONFIG4
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flash_cfg5_val:
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.word STNOR_GPMC_CONFIG5
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flash_cfg5_addr:
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.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
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pll_ctl_add:
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.word CM_CLKEN_PLL
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pll_div_add1:
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.word CM_CLKSEL1_PLL
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pll_div_add2:
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.word CM_CLKSEL_CORE
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pll_div_add3:
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.word CM_CLKSEL_WKUP
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pll_div_val3:
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.word (WKUP_RSM << 1)
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pll_div_add4:
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.word CM_CLKSEL_GFX
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pll_div_val4:
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.word (GFX_DIV << 0)
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pll_div_add5:
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.word CM_CLKSEL1_EMU
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pll_div_val5:
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.word CLSEL1_EMU_VAL
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go_to_speed_end:
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#endif
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
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!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
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ENTRY(lowlevel_init)
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ldr sp, SRAM_STACK
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str ip, [sp] /* stash ip register */
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mov ip, lr /* save link reg across call */
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#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
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/*
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* No need to copy/exec the clock code - DPLL adjust already done
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* in NAND/oneNAND Boot.
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*/
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ldr r1, =SRAM_CLK_CODE
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bl cpy_clk_code
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#endif /* NAND Boot */
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mov lr, ip /* restore link reg */
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ldr ip, [sp] /* restore save ip */
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/* tail-call s_init to setup pll, mux, memory */
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b s_init
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ENDPROC(lowlevel_init)
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#endif
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/* the literal pools origin */
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.ltorg
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REG_CONTROL_STATUS:
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.word CONTROL_STATUS
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SRAM_STACK:
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.word LOW_LEVEL_SRAM_STACK
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/* DPLL(1-4) PARAM TABLES */
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/*
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* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
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* OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
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* The values are defined for all possible sysclk and for ES1 and ES2.
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*/
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mpu_dpll_param:
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/* 12MHz */
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/* ES1 */
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.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
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/* ES2 */
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.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
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/* 3410 */
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.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
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/* 13MHz */
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/* ES1 */
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.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
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/* ES2 */
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.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
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/* 3410 */
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.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
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/* 19.2MHz */
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/* ES1 */
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.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
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/* ES2 */
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.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
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/* 3410 */
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.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
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/* 26MHz */
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/* ES1 */
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.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
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/* ES2 */
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.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
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/* 3410 */
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.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
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/* 38.4MHz */
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/* ES1 */
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.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
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/* ES2 */
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.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
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/* 3410 */
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.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
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.globl get_mpu_dpll_param
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get_mpu_dpll_param:
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adr r0, mpu_dpll_param
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mov pc, lr
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iva_dpll_param:
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/* 12MHz */
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/* ES1 */
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.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
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/* ES2 */
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.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
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/* 3410 */
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.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
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/* 13MHz */
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/* ES1 */
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.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
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/* ES2 */
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.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
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/* 3410 */
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.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
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/* 19.2MHz */
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/* ES1 */
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.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
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/* ES2 */
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.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
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/* 3410 */
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.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
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/* 26MHz */
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/* ES1 */
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.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
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/* ES2 */
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.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
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/* 3410 */
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.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
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/* 38.4MHz */
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/* ES1 */
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.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
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/* ES2 */
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.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
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/* 3410 */
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.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
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.globl get_iva_dpll_param
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get_iva_dpll_param:
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adr r0, iva_dpll_param
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mov pc, lr
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/* Core DPLL targets for L3 at 166 & L133 */
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core_dpll_param:
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/* 12MHz */
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/* ES1 */
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.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
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/* ES2 */
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.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
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/* 3410 */
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.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
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/* 13MHz */
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/* ES1 */
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.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
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/* ES2 */
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.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
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/* 3410 */
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.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
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/* 19.2MHz */
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/* ES1 */
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.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
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/* ES2 */
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.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
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/* 3410 */
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.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
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/* 26MHz */
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/* ES1 */
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.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
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/* ES2 */
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.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
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/* 3410 */
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.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
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/* 38.4MHz */
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/* ES1 */
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.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
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/* ES2 */
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.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
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/* 3410 */
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.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
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.globl get_core_dpll_param
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get_core_dpll_param:
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adr r0, core_dpll_param
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mov pc, lr
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/* PER DPLL values are same for both ES1 and ES2 */
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per_dpll_param:
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/* 12MHz */
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.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
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/* 13MHz */
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.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
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/* 19.2MHz */
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.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
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/* 26MHz */
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.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
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/* 38.4MHz */
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.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
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.globl get_per_dpll_param
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get_per_dpll_param:
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adr r0, per_dpll_param
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mov pc, lr
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/* PER2 DPLL values */
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per2_dpll_param:
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/* 12MHz */
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.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
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/* 13MHz */
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.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
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/* 19.2MHz */
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.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
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/* 26MHz */
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.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
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/* 38.4MHz */
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.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
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.globl get_per2_dpll_param
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get_per2_dpll_param:
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adr r0, per2_dpll_param
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mov pc, lr
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/*
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* Tables for 36XX/37XX devices
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*
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*/
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mpu_36x_dpll_param:
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/* 12MHz */
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.word 50, 0, 0, 1
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/* 13MHz */
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.word 600, 12, 0, 1
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/* 19.2MHz */
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|
.word 125, 3, 0, 1
|
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/* 26MHz */
|
|
.word 300, 12, 0, 1
|
|
/* 38.4MHz */
|
|
.word 125, 7, 0, 1
|
|
|
|
iva_36x_dpll_param:
|
|
/* 12MHz */
|
|
.word 130, 2, 0, 1
|
|
/* 13MHz */
|
|
.word 20, 0, 0, 1
|
|
/* 19.2MHz */
|
|
.word 325, 11, 0, 1
|
|
/* 26MHz */
|
|
.word 10, 0, 0, 1
|
|
/* 38.4MHz */
|
|
.word 325, 23, 0, 1
|
|
|
|
core_36x_dpll_param:
|
|
/* 12MHz */
|
|
.word 100, 2, 0, 1
|
|
/* 13MHz */
|
|
.word 400, 12, 0, 1
|
|
/* 19.2MHz */
|
|
.word 375, 17, 0, 1
|
|
/* 26MHz */
|
|
.word 200, 12, 0, 1
|
|
/* 38.4MHz */
|
|
.word 375, 35, 0, 1
|
|
|
|
per_36x_dpll_param:
|
|
/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
|
|
.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
|
|
.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
|
|
.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
|
|
.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
|
|
.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
|
|
|
|
per2_36x_dpll_param:
|
|
/* 12MHz */
|
|
.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
|
|
/* 13MHz */
|
|
.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
|
|
/* 19.2MHz */
|
|
.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
|
|
/* 26MHz */
|
|
.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
|
|
/* 38.4MHz */
|
|
.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
|
|
|
|
|
|
ENTRY(get_36x_mpu_dpll_param)
|
|
adr r0, mpu_36x_dpll_param
|
|
mov pc, lr
|
|
ENDPROC(get_36x_mpu_dpll_param)
|
|
|
|
ENTRY(get_36x_iva_dpll_param)
|
|
adr r0, iva_36x_dpll_param
|
|
mov pc, lr
|
|
ENDPROC(get_36x_iva_dpll_param)
|
|
|
|
ENTRY(get_36x_core_dpll_param)
|
|
adr r0, core_36x_dpll_param
|
|
mov pc, lr
|
|
ENDPROC(get_36x_core_dpll_param)
|
|
|
|
ENTRY(get_36x_per_dpll_param)
|
|
adr r0, per_36x_dpll_param
|
|
mov pc, lr
|
|
ENDPROC(get_36x_per_dpll_param)
|
|
|
|
ENTRY(get_36x_per2_dpll_param)
|
|
adr r0, per2_36x_dpll_param
|
|
mov pc, lr
|
|
ENDPROC(get_36x_per2_dpll_param)
|